JAJSKL8E june 2006 – october 2020 SN65LVDS302
PRODUCTION DATA
The SN65LVDS302 receiver performs error checking on the basis of a parity bit that is transmitted across the subLVDS interface from the transmitting device. Once the SN65LVDS302 detects the presence of the clock and the PLL has locked onto PCLK, then the parity is checked. Parity-error detection ensures detection of all single bit errors in one pixel and 50% of all multi-bit errors.
The parity bit covers the 27 bit data payload consisting of 24 bits of pixel data plus VS, HS, and DE. Odd Parity bit signalling is used. The parity error is output on the CPE pin. If the sum of the 27 data bits and the parity bit result in an odd number, the receive data are assumed to be valid. The CPE output is held low. If the sum equals an even number, parity error is declared. The CPE output indicates high for half a PCLK period. The CPE output is set with the data bit transition and cleared after 1/2 the data bit time. This allows counting every detected parity error with a simple counter connected to CPE.