Startseite Energiemanagement Linear- und Low-Dropout-Regler (LDO)
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Energiemanagement
Linear- und Low-Dropout-Regler (LDO)

TPS74901

AKTIV

Einstellbarer Spannungsregler mit extrem niedrigem Dropout, 3 A, niedrige VIN (0,8 V), mit Power Goo

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Datenblatt

TPS74901

AKTIV
Datenblatt Jetzt bestellen

Produktdetails

Output options Adjustable Output Iout (max) (A) 3 Vin (max) (V) 5.5 Vin (min) (V) 0.8 Vout (max) (V) 3.6 Vout (min) (V) 0.8 Noise (µVrms) 20 Iq (typ) (mA) 3 Thermal resistance θJA (°C/W) 34, 36 Rating Catalog Load capacitance (min) (µF) 2.2 Regulated outputs (#) 1 Features Enable, Power good, Soft start Accuracy (%) 2 PSRR at 100 KHz (dB) 28 Dropout voltage (Vdo) (typ) (mV) 60, 120 Operating temperature range (°C) -40 to 125
Output options Adjustable Output Iout (max) (A) 3 Vin (max) (V) 5.5 Vin (min) (V) 0.8 Vout (max) (V) 3.6 Vout (min) (V) 0.8 Noise (µVrms) 20 Iq (typ) (mA) 3 Thermal resistance θJA (°C/W) 34, 36 Rating Catalog Load capacitance (min) (µF) 2.2 Regulated outputs (#) 1 Features Enable, Power good, Soft start Accuracy (%) 2 PSRR at 100 KHz (dB) 28 Dropout voltage (Vdo) (typ) (mV) 60, 120 Operating temperature range (°C) -40 to 125
TO-263 (KTW) 7 153.924 mm² 10.1 x 15.24 VQFN (RGW) 20 25 mm² 5 x 5 VSON (DRC) 10 9 mm² 3 x 3
  • V OUT range: 0.8 V to 3.6 V
  • Ultra-low V IN range: 0.8 V to 5.5 V
  • V BIAS range: 2.7 V to 5.5 V
  • Low dropout: 120 mV (typical) at 3 A
  • Power-good (PG) output allows supply monitoring or provides a sequencing signal for other supplies
  • Accuracy over line, load, and temperature: 2%
  • Adjustable start-up in-rush control
  • V BIAS permits low V IN operation with good transient response
  • Stable with any output capacitor ≥ 2.2 µF
  • Packages:
    • Small, 3-mm × 3-mm × 1-mm VSON
    • 5-mm × 5-mm × 1-mm VQFN and DDPAK-7
  • Active high enable
  • V OUT range: 0.8 V to 3.6 V
  • Ultra-low V IN range: 0.8 V to 5.5 V
  • V BIAS range: 2.7 V to 5.5 V
  • Low dropout: 120 mV (typical) at 3 A
  • Power-good (PG) output allows supply monitoring or provides a sequencing signal for other supplies
  • Accuracy over line, load, and temperature: 2%
  • Adjustable start-up in-rush control
  • V BIAS permits low V IN operation with good transient response
  • Stable with any output capacitor ≥ 2.2 µF
  • Packages:
    • Small, 3-mm × 3-mm × 1-mm VSON
    • 5-mm × 5-mm × 1-mm VQFN and DDPAK-7
  • Active high enable

The TPS74901 low-dropout (LDO) linear regulator provides an easy-to-use, robust power management solution for a wide variety of applications. User-programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current during start-up. The soft-start is monotonic and designed for powering many different types of processors and application-specific integrated circuits (ASICs). The enable input and power-good output allow easy sequencing with external regulators. This complete flexibility allows a solution to be configured that meets the sequencing requirements of field-programmable gate arrays (FPGAs), digital signal processors (DSPs), and other applications with special start-up requirements.

A precision reference and error amplifier deliver 2% accuracy over load, line, temperature, and process. The device is stable with any type of capacitor ≥ 2.2 µF, and the device is fully specified from   –40°C to +125°C. The TPS74901 is offered in a small (3 mm × 3 mm) VSON package and a small (5-mm × 5-mm) VQFN package, yielding a highly compact total solution size. The device is also available in a DDPAK-7 package.

The TPS74901 low-dropout (LDO) linear regulator provides an easy-to-use, robust power management solution for a wide variety of applications. User-programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current during start-up. The soft-start is monotonic and designed for powering many different types of processors and application-specific integrated circuits (ASICs). The enable input and power-good output allow easy sequencing with external regulators. This complete flexibility allows a solution to be configured that meets the sequencing requirements of field-programmable gate arrays (FPGAs), digital signal processors (DSPs), and other applications with special start-up requirements.

A precision reference and error amplifier deliver 2% accuracy over load, line, temperature, and process. The device is stable with any type of capacitor ≥ 2.2 µF, and the device is fully specified from   –40°C to +125°C. The TPS74901 is offered in a small (3 mm × 3 mm) VSON package and a small (5-mm × 5-mm) VQFN package, yielding a highly compact total solution size. The device is also available in a DDPAK-7 package.
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Technische Dokumentation

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Typ Titel Datum
* Data sheet TPS74901 3-A, Low Dropout Linear Regulator With Programmable Soft-Start datasheet (Rev. J) PDF | HTML 24 Apr 2023
Application note LDO Noise Demystified (Rev. B) PDF | HTML 18 Aug 2020
Application note A Topical Index of TI LDO Application Notes (Rev. F) 27 Jun 2019
Selection guide Low Dropout Regulators Quick Reference Guide (Rev. P) 21 Mär 2018
Application note LDO PSRR Measurement Simplified (Rev. A) PDF | HTML 09 Aug 2017
Analog Design Journal Q2 2009 Issue Analog Applications Journal 01 Mai 2009
Analog Design Journal Taming linear-regulator inrush currents 01 Mai 2009
EVM User's guide TPS74901EVM-210 (Rev. B) 24 Jul 2008
EVM User's guide TPS74901EVM-210 14 Apr 2007

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Evaluierungsplatine

TPS74901EVM-210 — TPS74901 Evaluierungsmodul für einen einstellbaren 3-A-LDO-Spannungsregler mit niedrigem VIN-Wert (0

Das TPS74901EVM-210 erleichtert die Evaluierung des Low-Dropout-Linearregler-ICs TPS74901.

Diese Regler erfordern eine Vorspannung mit geringem Stromverbrauch, VBIAS, und eine Leistungseingangsspannung, VIN. Der Regler ist in der Lage, Ausgangsspannungen von bis zu 0,8 V und Ausgangsströme von bis (...)

Benutzerhandbuch: PDF
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Simulationsmodell

TPS74901 PSpice Transient Model (Rev. B)

SLIM031B.ZIP (60 KB) - PSpice Model
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Simulationsmodell

TPS74901 TINA-TI Transient Reference Design

SLIM257.TSC (94 KB) - TINA-TI Spice Model
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Simulationsmodell

TPS74901 TINA-TI Transient Spice Model

SLIM256.ZIP (35 KB) - TINA-TI Spice Model
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Simulationsmodell

TPS74901 Unencrypted PSpice Transient Model

SBVM634.ZIP (3 KB) - PSpice Model
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Referenzdesigns

TIDA-00431 — RF-Abtastungs-4-GSPS-ADC-Referenzdesign mit 8-GHz-DC-gekoppeltem Differenzialverstärker

Wideband radio frequency (RF) receivers allow greatly increased flexibility in radio designs. The wide instantaneous bandwidth allows flexible tuning without changing hardware and the ability to capture multiple channels at widely separated frequencies.

This reference design describes a wideband RF (...)

Design guide: PDF
Schaltplan: PDF
Referenzdesigns

TIDA-01017 — Highspeed-Mehrkanal-ADC-Taktreferenzdesign für Oszilloskope, Drahtlos-Tester und Radargeräte

The TIDA-01017 reference design demonstrates the performance of a clocking solution for a high speed multi-channel system, analyzed by measuring the channel to channel skew for the entire input frequency range of the RF sampling ADC. Channel to channel skew is critical for phased array radar and (...)
Design guide: PDF
Schaltplan: PDF
Referenzdesigns

TIDA-01015 — 4-GHz-Takt-Referenzdesign für 12-Bit-Highspeed-ADCs in digitalen Oszilloskopen und Drahtlos-Testern

The TIDA-01015 is a clocking solution reference design for high speed direct RF sampling GSPS ADCs. This design showcases the significance of the sampling clock to achieve high SNR for 2nd Nyquist zone input signal frequencies. ADC12J4000 is a 12-bit, 4-GSPS RF sampling ADC with 3-dB input (...)
Design guide: PDF
Schaltplan: PDF
Referenzdesigns

TIDA-00826 — 50-Ohm-2-GHz-Oszilloskop-Frontend – Referenzdesign

This reference design is part of an analog front-end for 50Ω-input oscilloscope application. System designers can readily use this evaluation platform to process input signals from DC to 2 GHz in both frequency-domain and time-domain applications.
Design guide: PDF
Schaltplan: PDF
Referenzdesigns

TIDA-00432 — Synchronisierung von JESD204B Gigasample-A/D-Wandlern mit Xilinx-Plattform für Phased-Array-Radarsys

This system level design shows how two ADC12J4000 evaluation modules (EVMs) can be synchronized together using a Xilinx VC707 platform. The design document describes the required hardware modifications and device configurations, including the clocking scheme. Example configuration files are shown (...)
Design guide: PDF
Schaltplan: PDF
Referenzdesigns

TIDA-00359 — Taktgebungs-Referenzdesign für GSPS-ADCs

Low cost, high performance clocking solution for GSPS data converters. This reference design discusses the use of a TRF3765, a low noise frequency synthesizer, generating the sampling clock for a 4 GSPS analog-to-digital converter (ADC12J4000). Experiments demonstrate data sheet comparable SNR and (...)
Design guide: PDF
Schaltplan: PDF
Gehäuse Pins Herunterladen
TO-263 (KTW) 7 Optionen anzeigen
VQFN (RGW) 20 Optionen anzeigen
VSON (DRC) 10 Optionen anzeigen
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Bestellen & Qualität

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  • Qualifikationszusammenfassung
  • Kontinuierliches Zuverlässigkeitsmonitoring
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