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UCC21330

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3kVRMS 4A/6A two-channel isolated gate driver with enable logic and programmable deadtime

Produktdetails

Number of channels 2 Isolation rating Basic Withstand isolation voltage (VISO) (Vrms) 3000 Transient isolation voltage (VIOTM) (VPK) 4242 Power switch IGBT, MOSFET, SiCFET Features Disable, High CMTI, Programmable dead time Output VCC/VDD (max) (V) 25 Output VCC/VDD (min) (V) 9.2 Input supply voltage (min) (V) 3 Input supply voltage (max) (V) 5.5 TI functional safety category Functional Safety-Capable Input threshold CMOS, TTL Operating temperature range (°C) -40 to 150 Rating Automotive Fall time (ns) 8 Undervoltage lockout (typ) (V) 8
Number of channels 2 Isolation rating Basic Withstand isolation voltage (VISO) (Vrms) 3000 Transient isolation voltage (VIOTM) (VPK) 4242 Power switch IGBT, MOSFET, SiCFET Features Disable, High CMTI, Programmable dead time Output VCC/VDD (max) (V) 25 Output VCC/VDD (min) (V) 9.2 Input supply voltage (min) (V) 3 Input supply voltage (max) (V) 5.5 TI functional safety category Functional Safety-Capable Input threshold CMOS, TTL Operating temperature range (°C) -40 to 150 Rating Automotive Fall time (ns) 8 Undervoltage lockout (typ) (V) 8
SOIC (D) 16 59.4 mm² 9.9 x 6
  • Universal: dual low-side, dual high-side or halfbridge driver

  • Junction temperature range –40 to +150°C
  • Up to 4A peak source and 6A peak sink output
  • Common-mode transient immunity (CMTI) greater than 125V/ns
  • Up to 25V VDD output drive supply
    • 8V VDD UVLO options
  • Switching parameters:
    • 33ns typical propagation delay
    • 5ns maximum pulse-width distortion
    • 10µs maximum VDD power-up delay
  • UVLO protection for all power supplies
  • Fast disable for power sequencing
  • Universal: dual low-side, dual high-side or halfbridge driver

  • Junction temperature range –40 to +150°C
  • Up to 4A peak source and 6A peak sink output
  • Common-mode transient immunity (CMTI) greater than 125V/ns
  • Up to 25V VDD output drive supply
    • 8V VDD UVLO options
  • Switching parameters:
    • 33ns typical propagation delay
    • 5ns maximum pulse-width distortion
    • 10µs maximum VDD power-up delay
  • UVLO protection for all power supplies
  • Fast disable for power sequencing

The UCC21330 is an isolated dual channel gate driver family with programmable dead time and wide temperature range. It is designed with 4A peak-source and 6A peak-sink current to drive power MOSFET, SiC, GaN, and IGBT transistors.

The UCC21330 can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver. The input side is isolated from the two output drivers by a 5kVRMS isolation barrier, with a minimum of 125V/ns common-mode transient immunity (CMTI).

Protection features include: resistor programmable dead time, disable feature to shut down both outputs simultaneously, and integrated de-glitch filter that rejects input transients shorter than 5ns. All supplies have UVLO protection.

With all these advanced features, the UCC21330 device enables high efficiency, high power density, and robustness in a wide variety of power applications.

The UCC21330 is an isolated dual channel gate driver family with programmable dead time and wide temperature range. It is designed with 4A peak-source and 6A peak-sink current to drive power MOSFET, SiC, GaN, and IGBT transistors.

The UCC21330 can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver. The input side is isolated from the two output drivers by a 5kVRMS isolation barrier, with a minimum of 125V/ns common-mode transient immunity (CMTI).

Protection features include: resistor programmable dead time, disable feature to shut down both outputs simultaneously, and integrated de-glitch filter that rejects input transients shorter than 5ns. All supplies have UVLO protection.

With all these advanced features, the UCC21330 device enables high efficiency, high power density, and robustness in a wide variety of power applications.

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Technische Dokumentation

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* Data sheet UCC21330x 4A, 6A, 3kVRMS Isolated Dual-Channel Gate Driver datasheet PDF | HTML 26 Jan 2024

Design und Entwicklung

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Evaluierungsplatine

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