SBASAU7C December   2024  – July 2025 ADC3548 , ADC3549

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications (ADC3548 - 250 MSPS)
    8. 6.8  Electrical Characteristics - AC Specifications (ADC3549 - 500 MSPS)
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics - ADC3548 (250MSPS)
    11. 6.11 Typical Characteristics - ADC3549 (500MSPS)
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs
        1. 8.3.1.1 Nyquist Zone Selection
        2. 8.3.1.2 Analog Front End Design
      2. 8.3.2 Sampling Clock
        1. 8.3.2.1 Multi-Chip Synchronization
        2. 8.3.2.2 SYSREF Monitor
      3. 8.3.3 Time-Stamp
      4. 8.3.4 Overrange
      5. 8.3.5 External Voltage Reference
      6. 8.3.6 Digital Gain
      7. 8.3.7 Decimation Filter
        1. 8.3.7.1 Uncommon Decimation Ratios
        2. 8.3.7.2 Decimation Filter Response
        3. 8.3.7.3 Decimation Filter Configuration
        4. 8.3.7.4 Numerically Controlled Oscillator (NCO)
      8. 8.3.8 Digital Interface
        1. 8.3.8.1 Parallel LVDS (SDR) - Default
        2. 8.3.8.2 Parallel LVDS (DDR)
        3. 8.3.8.3 SLVDS with Decimation
          1. 8.3.8.3.1 SLVDS - Status Bit Insertion
        4. 8.3.8.4 Output Data Format
        5. 8.3.8.5 32-bit Output Resolution
        6. 8.3.8.6 Output Scrambler
        7. 8.3.8.7 Output MUX
        8. 8.3.8.8 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low Latency Mode
      2. 8.4.2 Power Down Mode
    5. 8.5 Programming
      1. 8.5.1 GPIO Programming
      2. 8.5.2 Register Write
      3. 8.5.3 Register Read
      4. 8.5.4 Device Programming
      5. 8.5.5 Register Map
      6. 8.5.6 Register Description
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Wideband Spectrum Analyzer
      2. 9.2.2 Design Requirements
        1. 9.2.2.1 Input Signal Path
        2. 9.2.2.2 Clocking
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Sampling Clock
      4. 9.2.4 Application Performance Plots
      5. 9.2.5 Initialization Set Up
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.3 Time-Stamp

The ADC354x includes a time-stamp feature which enables tagging a specific sample on the analog input in DDC bypass mode. When enabling the feature (via SPI write), a logic low-to-high transition on the GPIO/SYSREF pin is registered on the rising edge of the sampling clock. The time stamp signal is output on the lane DOUT2 (LSB) however it is not latency matched with the output data. The time-stamp feature is available with SDR and DDR LVDS.

As shown in Figure 8-19the time stamp signal is indicated 35 clock cycles ahead of the output data:

  • Latency output data: 43 clock cycles
  • Latency time stamp output: 8 clock cycles
ADC3548 ADC3549 Timing Diagram - Time-Stamp Output with SDR LVDS Figure 8-19 Timing Diagram - Time-Stamp Output with SDR LVDS
Table 8-4 Example register writes to enable time stamp on pin GPIO0
ADDR DATA DESCRIPTION
0x146 0x00 Enable SYSREF on pin GPIO0.
0x162 0xC0 Enable time stamp function replacing the LSB.