SBASAU7C December   2024  – July 2025 ADC3548 , ADC3549

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications (ADC3548 - 250 MSPS)
    8. 6.8  Electrical Characteristics - AC Specifications (ADC3549 - 500 MSPS)
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics - ADC3548 (250MSPS)
    11. 6.11 Typical Characteristics - ADC3549 (500MSPS)
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs
        1. 8.3.1.1 Nyquist Zone Selection
        2. 8.3.1.2 Analog Front End Design
      2. 8.3.2 Sampling Clock
        1. 8.3.2.1 Multi-Chip Synchronization
        2. 8.3.2.2 SYSREF Monitor
      3. 8.3.3 Time-Stamp
      4. 8.3.4 Overrange
      5. 8.3.5 External Voltage Reference
      6. 8.3.6 Digital Gain
      7. 8.3.7 Decimation Filter
        1. 8.3.7.1 Uncommon Decimation Ratios
        2. 8.3.7.2 Decimation Filter Response
        3. 8.3.7.3 Decimation Filter Configuration
        4. 8.3.7.4 Numerically Controlled Oscillator (NCO)
      8. 8.3.8 Digital Interface
        1. 8.3.8.1 Parallel LVDS (SDR) - Default
        2. 8.3.8.2 Parallel LVDS (DDR)
        3. 8.3.8.3 SLVDS with Decimation
          1. 8.3.8.3.1 SLVDS - Status Bit Insertion
        4. 8.3.8.4 Output Data Format
        5. 8.3.8.5 32-bit Output Resolution
        6. 8.3.8.6 Output Scrambler
        7. 8.3.8.7 Output MUX
        8. 8.3.8.8 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low Latency Mode
      2. 8.4.2 Power Down Mode
    5. 8.5 Programming
      1. 8.5.1 GPIO Programming
      2. 8.5.2 Register Write
      3. 8.5.3 Register Read
      4. 8.5.4 Device Programming
      5. 8.5.5 Register Map
      6. 8.5.6 Register Description
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Wideband Spectrum Analyzer
      2. 9.2.2 Design Requirements
        1. 9.2.2.1 Input Signal Path
        2. 9.2.2.2 Clocking
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Sampling Clock
      4. 9.2.4 Application Performance Plots
      5. 9.2.5 Initialization Set Up
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.2 Sampling Clock

The sampling clock input is designed to be driven differentially with external AC coupling and termination. The ADC provides internal common mode voltage biasing as shown in Figure 8-8.

ADC3548 ADC3549 Sampling Clock Input Circuitry Figure 8-8 Sampling Clock Input Circuitry

The internal sampling clock path was designed for low residual phase noise contribution. The sampling clock circuitry requires a dedicated, low noise power supply for best phase noise and jitter performance. The internal residual clock phase noise is also sensitive to clock amplitude.

The internal residual clock noise consists of two components - phase noise and amplitude noise as shown in Table 8-1. The phase noise scales with input frequency and sampling rate (20*log(fIN/FS)) while the amplitude noise does not scale.

Table 8-1 Phase and Amplitude Noise at 500MHz
Frequency Offset (MHz) Phase Noise (dBc/Hz) Amplitude Noise (dBc/Hz)
0.001 -130 -129
0.01 -140 -139
0.1 -150 -149
1 -160 -159
3 -165 -164
10 -165 -164

Figure 8-9 and Figure 8-10 show the phase and amplitude noise at three different input frequencies.

ADC3548 ADC3549 Phase Noise ExamplesFigure 8-9 Phase Noise Examples
ADC3548 ADC3549 Amplitude Noise ExamplesFigure 8-10 Amplitude Noise Examples

The internal clock noise is also dependent on the external clock amplitude. Figure 8-11 to Figure 8-14 show the expected AC performance for different input frequencies across clock amplitude.

ADC3548 ADC3549 AC vs Clock Amplitude
FS = 500MSPS FIN = 100MHz AIN = -1dBFS
Figure 8-11 AC vs Clock Amplitude
ADC3548 ADC3549 AC vs Clock Amplitude
FS = 250MSPS FIN = 100MHz AIN = -1dBFS
Figure 8-13 AC vs Clock Amplitude
ADC3548 ADC3549 AC vs Clock Amplitude
FS = 500MSPS FIN = 400MHz AIN = -1dBFS
Figure 8-12 AC vs Clock Amplitude
ADC3548 ADC3549 AC vs Clock Amplitude
FS = 250MSPS FIN = 240MHz AIN = -1dBFS
Figure 8-14 AC vs Clock Amplitude