CS selects the ADS1291, ADS1292, and ADS1292R for SPI communication. CS must remain low for the entire duration of the serial communication. After the serial communication is finished, always wait four or more tCLK cycles before taking CS high. When CS is taken high, the serial interface is reset, SCLK and DIN are ignored, and DOUT enters a high-impedance state. DRDY asserts when data conversion is complete, regardless of whether CS is high or low.