The settling time (tSETTLE) is the time it takes for the converter to output fully settled data when the START signal is pulled high. Once START is pulled high, DRDY is also pulled high. The next DRDY falling edge indicates that data are ready. Figure 48 shows the timing diagram and Table 13 shows the settling time for different data rates. The settling time depends on fCLK and the decimation ratio (controlled by the DR[2:0] bits in the CONFIG1 register). Refer to Table 10 for the settling time as a function of tMOD. Note that when START is held high and there is a step change in the input signal, it takes 3 tDR for the filter to settle to the new value. Settled data are available on the fourth DRDY pulse. Settling time number uncertainty is one tMOD cycle. Therefore, it is recommended to add one tMOD cycle delay before issuing SCLK to retrieve data.