The ADS1291, ADS1292, and ADS1292R provide two different methods for device clocking: internal and external. Internal clocking is ideally suited for low-power, battery-powered systems. The internal oscillator is trimmed for accuracy at room temperature. Over the specified temperature range the accuracy varies; see the Electrical Characteristics. Clock selection is controlled by the CLKSEL pin and the CLK_EN register bit.
The CLKSEL pin selects either the internal or external clock. The CLK_EN bit in the CONFIG2 register enables and disables the oscillator clock to be output in the CLK pin. A truth table for these two pins is shown in Table 9. The CLK_EN bit is useful when multiple devices are used in a daisy-chain configuration. It is recommended that during power-down the external clock be shut down to save power.
|CLKSEL PIN||CONFIG2.CLK_EN BIT||CLOCK SOURCE||CLK PIN STATUS|
|0||X||External clock||Input: external clock|
|1||0||Internal clock oscillator||3-state|
|1||1||Internal clock oscillator||Output: internal clock oscillator|
The ADS1291, ADS1292, and ADS1292R have the option to choose between two different external clock frequencies (512 kHz or 2.048 MHz). This frequency is selected by setting the CLK_DIV bit (bit 6) in the LOFF_STAT register. The modulator must be clocked at 128 kHz, regardless of the external clock frequency. Figure 32 shows the relationship between the external clock (fCLK) and the modulator clock (fMOD). The default mode of operation is fCLK = 512 kHz. The higher frequency option has been provided to allow the SPI to run at a higher speed. SCLK can be only twice the speed of fCLK during a register read or write, see section on sending multi-byte commands. Having the 2.048 MHz option allows for register read and writes to be performed at SCLK speeds up to 4.096 MHz.