The ADS1291 and ADS1292 provide flexibility for PACE detection by using an external hardware. The external hardware approach is made possible by bringing out the output of the PGA at pins: PGA1P, PGA1N and PGA2P, PGA2N.
External hardware circuitry can be used to detect the presence of the pulse. The output of the PACE detection logic can then be fed into the device through one of the GPIO pins. The GPIO data are transmitted through the SPI port and loaded 2 tCLKs before DRDY goes low.
When in pace detection mode, the chopping ripple can interfere with pace detect in hardware. It is therefore preffered to chop thee PGA at a higher frequency (32 kHz or 64 kHz). The RC filter at the PGA output, suppresses this ripple to a reasonable level. Additionally, suppression can be obtained with an additional RC stage. The trade-off with chopping the PGA at a higher frequency is an increase in the input bias current. Figure 6 shows bias current versus input voltage for three different chop frequencies.