The PGA is a differential input or differential output amplifier, as shown in Figure 22. It has seven gain settings (1, 2, 3, 4, 6, 8, and 12) that can be set by writing to the CHnSET register (see the CH1SET and CH2SET Registers in the Register Map section for details). The ADS1291, ADS1292, and ADS1292R have CMOS inputs and hence have negligible current noise.
The PGA resistor string that implements the gain has 360 kΩ of resistance for a gain of 6. This resistance provides a current path across the outputs of the PGA in the presence of a differential input signal. This current is in addition to the quiescent current specified for the device in the presence of a differential signal at the input. The PGA output is filtered by an RC filter before it goes to the ADC. The filter is formed by an internal resistor RS = 2 kΩ and an external capacitor CFILTER (4.7 nF, typical). This filter acts as an anti-aliasing filter with the –3-dB bandwidth of 8.4 kHz. The internal RS resistor is accurate to 15% so actual bandwidth will vary. This RC filter also suppresses the glitch at the PGA output caused by ADC sampling. The minimum value of CEXT that can be used is 4 nF. A larger value CFILTER capacitor can be used for increased attenuation at higher frequencies for anti-aliasing purposes. If channel 1 of the ADS1292R is used for respiration measurement, then a 4.7-nF external capacitor is recommended. The tradeoff is that a larger capacitor value gives degraded THD performance. See Figure 23 for a diagram explaining the THD versus CFILTER value for a 10-Hz input signal.
Special care must be taken in PCB layout to minimize the parasitic capacitance CP1 / CP2. The absolute value of these capacitances must be less than 20 pF. Ideally, CFILTER should be placed right at the pins to minimize these capacitors. Mismatch between these capacitors will lead to CMRR degradation. Assuming everything else is perfectly matched, the 60-Hz CMRR as a function of this mismatch is given by Equation 4.
where ΔCP = CP1 – CP2
For example, a mismatch of 20 pF with a gain of 6 limits the CMRR to 112 dB. If ΔCP is small, then the CMRR is limited by the PGA itself and is as specified in the Electrical Characteristics table. The PGA are chopped internally at either 8, 32, or 64 kSPS, as determined by the CHOP bits (see the RLD_SENS: Right Leg Drive Sense Selection register, bits[7:6]). The digital decimation filter filters out the chopping ripple in the normal path so the chopping ripple is not a concern. If PGA output is used for hardware PACE detection, the chopping ripple must be filtered. First-order filtering is provided by the RC filter at the PGA output. Additional filtering may be needed to suppress the chopping ripple. If the PGA output is routed to other circuitry, a 20-kΩ series resistance must be added in the path near the CFILTER capacitor. The routing should be matched to maintain the CMRR performance.