The PWDN/RESET pins are shared. If PWDN/RESET is held low for longer than 29 fMOD clock cycles, the device is powered down. The implementation is such that the device is always reset when PWDN/RESET makes a transition from high to low. If the device is powered down it is reset first and then if 210 clock elapses it is powered down. Hence, all registers must be rewritten after power up.
There are two methods to reset the ADS1291, ADS1292, and ADS1292R: pull the PWDN/RESET pin low, or send the RESET opcode command. When using the PWDN/RESET pin, take it low to force a reset. Make sure to follow the minimum pulse width timing specifications before taking the PWDN/RESET pin back high. The RESET command takes effect on the eighth SCLK falling edge of the opcode command. On reset it takes 18 tCLK cycles to complete initialization of the configuration registers to the default states and start the conversion cycle. Note that an internal RESET is automatically issued to the digital filter whenever the CONFIG1, RESP1, and RESP2 registers are set to a new value with a WREG command.