SLVSIN3 May   2025 ADS9117 , ADS9118 , ADS9119

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Thermal Information
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements
    7. 6.7  Switching Characteristics
    8. 6.8  Timing Diagrams
    9. 6.9  Typical Characteristics: All Devices
    10. 6.10 Typical Characteristics: ADS9119
    11. 6.11 Typical Characteristics: ADS9118
    12. 6.12 Typical Characteristics: ADS9117
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
      2. 7.3.2 Analog Input Bandwidth
      3. 7.3.3 ADC Transfer Function
      4. 7.3.4 Reference Voltage
      5. 7.3.5 Temperature Sensor
      6. 7.3.6 Data Averaging
      7. 7.3.7 Digital Down Converter
      8. 7.3.8 Data Interface
        1. 7.3.8.1 Data Frame Width
        2. 7.3.8.2 ADC Output Data Randomizer
        3. 7.3.8.3 Synchronizing Multiple ADCs
        4. 7.3.8.4 Test Patterns for Data Interface
          1. 7.3.8.4.1 Fixed Pattern
          2. 7.3.8.4.2 Alternating Test Pattern
          3. 7.3.8.4.3 Digital Ramp
      9. 7.3.9 ADC Sampling Clock Input
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset
      2. 7.4.2 Power-Down Options
      3. 7.4.3 Normal Operation
      4. 7.4.4 Initialization Sequence
    5. 7.5 Programming
      1. 7.5.1 Register Write
      2. 7.5.2 Register Read
      3. 7.5.3 Multiple Devices: Daisy-Chain Topology for SPI Configuration
        1. 7.5.3.1 Register Write With Daisy-Chain
        2. 7.5.3.2 Register Read With Daisy-Chain
  9. 8 Register Map
    1. 8.1 Register Bank 0
    2. 8.2 Register Bank 1
    3. 8.3 Register Bank 2
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Data Acquisition (DAQ) Circuit for a ≤20kHz Input Signal Bandwidth
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Data Acquisition (DAQ) Circuit for a ≤100kHz Input Signal Bandwidth
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Application Curves
      3. 9.2.3 Data Acquisition (DAQ) Circuit for a ≤1MHz Input Signal Bandwidth
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

Figure 5-1 RHA Package, 6mm × 6mm, 40-Pin VQFN (Top View)
Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
AINM4INegative analog input for ADC.
AINP3IPositive analog input for ADC.
AVDD_5V1, 10P5V analog power-supply pin.
CS17IChip-select input pin for the interface configuration; active low.
DCLKM23ONegative differential data clock output. Connect a 100Ω resistor between DCLKP and DCLKM close to the receiver.
DCLKP24OPositive differential data clock output. Connect a 100Ω resistor between DCLKP and DCLKM close to the receiver.
DOUTM27ONegative differential data output. Connect a 100Ω resistor between DOUTP and DOUTM close to the receiver.
DOUTP28OPositive differential data output. Connect a 100Ω resistor between DOUTP and DOUTM close to the receiver.
FCLKM29ONegative differential data frame clock output. Connect a 100Ω resistor between FCLKP and FCLKM close to the receiver.
FCLKP30OPositive differential data frame clock output. Connect a 100Ω resistor between FCLKP and FCLKM close to the receiver.
GND2, 7, 8, 9, 11, 12, 15, 34, 38PGround.
NC 25, 26 – No external connection. Leave floating.
PWDN22IPower-down control; active low. Connect to VDD_1V8 if unused.
REFIO39I/OInternal reference voltage output. External reference voltage input. Connect a 10μF decoupling capacitor to REFM.
REFM6, 40PReference ground. Connect to GND.
RESET21IReset input; active low. Connect to VDD_1V8 if unused.
SCLK18ISerial clock input for the interface configuration.
SDI/EXTREF19ISDI is a multifunction logic input; pin function is determined by the SPI_EN pin. SDI has an internal 100kΩ pulldown resistor to GND. SPI_EN = 0b: SDI is the logic input to select between the internal or external reference. Connect SDI to GND for the external reference. Connect SDI to IOVDD for the internal reference. SPI_EN = 1b: Serial data input for the interface configuration.
SDO20OSerial data output for the configuration interface.
SMPL_CLKM31IADC sampling clock input. Negative differential input for the LVDS sampling clock. Connect this pin to GND for the CMOS sampling clock.
SMPL_CLKP32IADC sampling clock input. Positive differential input for the LVDS sampling clock. Clock input for the CMOS sampling clock.
SMPL_SYNC33ISynchronization input for internal averaging filter.
Connect to GND if unused. See the Synchronizing Multiple ADCs section on how to use the SMPL_SYNC pin.
SPI_EN16IControl to enable the SPI configuration; active high.
Connect a pullup resistor to VDD_1V8 to keep the configuration interface enabled. Connect to GND if the SPI configuration is unused.
Thermal Pad—PExposed thermal pad. Connect to GND.
VCMOUT5OCommon-mode voltage output. Use VCMOUT to set the common-mode voltage at the ADC inputs. Connect a 1μF decoupling capacitor to GND.
VDD_1V813, 14, 35, 36, 37P1.8V power-supply. Connect 1μF and 0.1μF decoupling capacitors to GND.
(1) I = input, O = output, I/O = input or output, G = ground, P = power.