SLUSFQ0C November   2024  – September 2025 BQ27Z758

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configurations and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
      1. 5.5.1 Supply Current
      2. 5.5.2 Common Analog (LDO, LFO, HFO, REF1, REF2, I-WAKE)
      3. 5.5.3 Battery Protection (CHG, DSG)
      4. 5.5.4 Cell Sensing Output (BAT_SP, BAT_SN)
      5. 5.5.5 Gauge Measurements (ADC, CC, Temperature)
      6. 5.5.6 Flash Memory
    6. 5.6 Digital I/O: DC Characteristics
    7. 5.7 Digital I/O: Timing Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  BQ27Z758 Processor
      2. 6.3.2  Battery Parameter Measurements
        1. 6.3.2.1 Coulomb Counter (CC) and Digital Filter
        2. 6.3.2.2 ADC Multiplexer
        3. 6.3.2.3 Analog-to-Digital Converter (ADC)
        4. 6.3.2.4 Internal Temperature Sensor
        5. 6.3.2.5 External Temperature Sensor Support
      3. 6.3.3  Power Supply Control
      4. 6.3.4  ENAB Pin
      5. 6.3.5  Bus Communication Interface
      6. 6.3.6  Low Frequency Oscillator
      7. 6.3.7  High Frequency Oscillator
      8. 6.3.8  1.8V Low Dropout Regulator
      9. 6.3.9  Internal Voltage References
      10. 6.3.10 Overcurrent in Discharge Protection
      11. 6.3.11 Overcurrent in Charge Protection
      12. 6.3.12 Short-Circuit Current in Discharge Protection
      13. 6.3.13 Primary Protection Features
      14. 6.3.14 Battery Sensing
      15. 6.3.15 Gas Gauging
      16. 6.3.16 Zero Volt Charging (ZVCHG)
      17. 6.3.17 Charge Control Features
      18. 6.3.18 Authentication
    4. 6.4 Device Functional Modes
      1. 6.4.1 Lifetime Logging Features
      2. 6.4.2 Configuration
        1. 6.4.2.1 Coulomb Counting
        2. 6.4.2.2 Cell Voltage Measurements
        3. 6.4.2.3 Auto Calibration
        4. 6.4.2.4 Temperature Measurements
  8. 7 Applications and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Design Requirements (Default)
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Changing Design Parameters
      3. 7.2.3 Calibration Process
      4. 7.2.4 Gauging Data Updates
        1. 7.2.4.1 Application Curve
      5. 7.2.5 ESD Mitigation
    3. 7.3 Power Supply Requirements
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Third-Party Products Disclaimer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Orderable, and Packaging Information
    1.     PACKAGE OPTION ADDENDUM
    2. 10.1 Tape and Reel Information
    3. 10.2 Mechanical Data

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YAH|15
Thermal pad, mechanical data (Package|Pins)

5.7 Digital I/O: Timing Characteristics

PARAMETERTEST CONDITIONSMINNOMMAXUNIT
I2C TIMING — 100kHz
fSCLClock Operating FrequencySCL duty cycle = 50%100kHz
tHD:STASTART Condition Hold Time4.0µs
tLOWLow period of the SCL Clock4.7µs
tHIGHHigh period of the SCL Clock4.0µs
tSU:STASetup repeated START4.7µs
tHD:DATData hold time (SDA input)0ns
tSU:DATData setup time (SDA input)250ns
trClock Rise Time10% to 90%1000ns
tfClock Fall Time90% to 10%300ns
tSU:STOSetup time STOP Condition4.0µs
tBUFBus free time STOP to START4.7µs
I2C TIMING — 400kHz
fSCLClock Operating FrequencySCL duty cycle = 50%400kHz
tHD:STASTART Condition Hold Time0.6µs
tLOWLow period of the SCL Clock1.3µs
tHIGHHigh period of the SCL Clock600ns
tSU:STASetup repeated START600ns
tHD:DATData hold time (SDA input)0ns
tSU:DATData setup time (SDA input)100ns
trClock Rise Time10% to 90%300ns
tfClock Fall Time90% to 10%300ns
tSU:STOSetup time STOP Condition0.6µs
tBUFBus free time STOP to START1.3µs
HDQ Timing
tBBreak Time190µs
tBRBreak Recovery Time40µs
tHW1Host Write 1 TimeHost drives HDQ0.550µs
tHW0Host Write 0 TimeHost drives HDQ86145µs
tCYCHCycle Time, Host to devicedevice drives HDQ190µs
tCYCDCycle Time, device to Hostdevice drives HDQ190205250µs
tDW1Device Write 1 Timedevice drives HDQ3250µs
tDW0Device Write 0 Timedevice drives HDQ80145µs
tRSPSDevice Response Timedevice drives HDQ190950µs
tTRNDHost Turn Around TimeHost drives HDQ after device drives HDQ250µs
tRISEHDQ Line Rising Time to Logic 11.8µs
tRSTHDQ ResetHost drives HDQ low before device reset2.2s
BQ27Z758 I2C TimingFigure 5-1 I2C Timing
BQ27Z758 HDQ TimingFigure 5-2 HDQ Timing