SLUSFQ0C November   2024  – September 2025 BQ27Z758

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configurations and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
      1. 5.5.1 Supply Current
      2. 5.5.2 Common Analog (LDO, LFO, HFO, REF1, REF2, I-WAKE)
      3. 5.5.3 Battery Protection (CHG, DSG)
      4. 5.5.4 Cell Sensing Output (BAT_SP, BAT_SN)
      5. 5.5.5 Gauge Measurements (ADC, CC, Temperature)
      6. 5.5.6 Flash Memory
    6. 5.6 Digital I/O: DC Characteristics
    7. 5.7 Digital I/O: Timing Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  BQ27Z758 Processor
      2. 6.3.2  Battery Parameter Measurements
        1. 6.3.2.1 Coulomb Counter (CC) and Digital Filter
        2. 6.3.2.2 ADC Multiplexer
        3. 6.3.2.3 Analog-to-Digital Converter (ADC)
        4. 6.3.2.4 Internal Temperature Sensor
        5. 6.3.2.5 External Temperature Sensor Support
      3. 6.3.3  Power Supply Control
      4. 6.3.4  ENAB Pin
      5. 6.3.5  Bus Communication Interface
      6. 6.3.6  Low Frequency Oscillator
      7. 6.3.7  High Frequency Oscillator
      8. 6.3.8  1.8V Low Dropout Regulator
      9. 6.3.9  Internal Voltage References
      10. 6.3.10 Overcurrent in Discharge Protection
      11. 6.3.11 Overcurrent in Charge Protection
      12. 6.3.12 Short-Circuit Current in Discharge Protection
      13. 6.3.13 Primary Protection Features
      14. 6.3.14 Battery Sensing
      15. 6.3.15 Gas Gauging
      16. 6.3.16 Zero Volt Charging (ZVCHG)
      17. 6.3.17 Charge Control Features
      18. 6.3.18 Authentication
    4. 6.4 Device Functional Modes
      1. 6.4.1 Lifetime Logging Features
      2. 6.4.2 Configuration
        1. 6.4.2.1 Coulomb Counting
        2. 6.4.2.2 Cell Voltage Measurements
        3. 6.4.2.3 Auto Calibration
        4. 6.4.2.4 Temperature Measurements
  8. 7 Applications and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Design Requirements (Default)
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Changing Design Parameters
      3. 7.2.3 Calibration Process
      4. 7.2.4 Gauging Data Updates
        1. 7.2.4.1 Application Curve
      5. 7.2.5 ESD Mitigation
    3. 7.3 Power Supply Requirements
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Third-Party Products Disclaimer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Orderable, and Packaging Information
    1.     PACKAGE OPTION ADDENDUM
    2. 10.1 Tape and Reel Information
    3. 10.2 Mechanical Data

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YAH|15
Thermal pad, mechanical data (Package|Pins)

5.5.2 Common Analog (LDO, LFO, HFO, REF1, REF2, I-WAKE)

Unless otherwise noted, characteristics noted under conditions of TA = –40 to 85℃
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
INTERNAL 1.8V LDO (REG18)
VREG18 Regulator output voltage 1.6 1.8 2.0 V
ΔVREG18TEMP Regulator output change with temperature ΔVBAT/ΔTA, IREG18 = 10mA –1.2% +1.2%
ΔVREG18LINE Line regulation –0.8% 0.8%
ΔVREG18LOAD Load regulation IREG18 = 16mA –1.5% 1.5%
ISHORT Short Circuit Current Limit VREG18 = 0V 18 60 mA
PSRRREG18 Power Supply Rejection Ratio ΔVBAT/ΔVREG18, IREG18 = 10mA, VBAT > 2.5V, f = 10Hz 50 dB
VPORth POR threshold Rising Threshold 1.55 1.65 1.75 V
VPORhy POR hysteresis 0.1 V
VENAB ENAB turn-on voltage for LDO (1) Active low falling threshold 0.4 V
RENAB ENAB pin pullup resistance (1) Internal pull-up to VDD 0.7 1 1.3 MΩ
VSTARTUP Minimum PACK pin turn-on voltage for LDO (1) 2 V
LOW FREQUENCY INTERNAL OSCILLATOR (LFO)
fLFO LFO Operating frequency Normal operating mode 65.536 kHz
fLFO(ERR) LFO Frequency error –2.5% +2.5%
fLFO32 LFO operating frequency Low power mode 32.768 kHz
fLFO32(ERR) LFO frequency error –5% +5%
HIGH FREQUENCY INTERNAL OSCILLATOR (HFO)
fHFO HFO operating frequency 16.78 MHz
fHFO(ERR) HFO frequency error TA = –20°C to 70°C –2.5% 2.5%
TA = –40°C to 85°C –3.5% 3.5%
tHFOSTART HFO start-up time TA = –40°C to 85°C, CLKCTL[HFRAMP] = 1, oscillator frequency within +/- 3% of nominal frequency or a power-on reset 4 ms
VOLTAGE REFERENCE1 (VREF1)
VREF1 Internal reference voltage REF1 is for protection circuits, LDO, and CC 1.195 1.21 1.227 V
VREF1_DRIFT Internal Reference Voltage Drift –80 +80 PPM/°C
VOLTAGE REFERENCE2 (VREF2)
VREF2 Internal Reference Voltage REF2 is for the ADC 1.2 1.21 1.22 V
VREF2_DRIFT Internal Reference Voltage Drift –20 +20 PPM/°C
WAKE-UP COMPARATOR (I-WAKE)
VWAKE Sense resistor voltage threshold range to wake-up gauge from low-power states(2) 500µV step. Data Flash firmware default is 2mV typical –1.5 –2.0 –2.5 mV
IWAKE Effective wake-up current threshold range Ideal RSNS = 1mΩ –1000 –3000 mA
Ideal RSNS = 2mΩ –500 –1500
Ideal RSNS = 5mΩ –200 –600
VWAKE_ACC Wake-up detection accuracy(2) –250 250 µV
tWAKE I-WAKE detection delay options(1) Configurable with two delay options. Data Flash firmware default is 12ms typical 9.6 12 14.4 ms
19.2 24 28.8
(1) Specified by design
(2) Data flash is configurable in FULL ACCESS mode and locked in SEALED. Accuracy is certified by factory trim at specified default threshold. A change in the factory threshold requires device calibration in the field.