SWRS272C april   2023  – june 2023 CC2340R5

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Revision History
  7. 6 Device Comparison
  8. 7 Pin Configuration and Functions
    1. 7.1 Pin Diagram – RKP Package (Top View)
    2. 7.2 Signal Descriptions – RKP Package
    3. 7.3 Connections for Unused Pins and Modules – RKP Package
    4. 7.4 Pin Diagram – RGE Package (Top View)
    5. 7.5 Signal Descriptions – RGE Package
    6. 7.6 Connections for Unused Pins and Modules – RGE Package
    7. 7.7 RKP and RGE Peripheral Pin Mapping
    8. 7.8 RKP and RGE Peripheral Signal Descriptions
  9. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  DCDC
    5. 8.5  Global LDO (GLDO)
    6. 8.6  Power Supply and Modules
    7. 8.7  Battery Monitor
    8. 8.8  Temperature Sensor
    9. 8.9  Power Consumption - Power Modes
    10. 8.10 Power Consumption - Radio Modes
    11. 8.11 Nonvolatile (Flash) Memory Characteristics
    12. 8.12 Thermal Resistance Characteristics
    13. 8.13 RF Frequency Bands
    14. 8.14 Bluetooth Low Energy - Receive (RX)
    15. 8.15 Bluetooth Low Energy - Transmit (TX)
    16. 8.16 Proprietary Radio Modes
    17. 8.17 2.4 GHz RX/TX CW
    18. 8.18 Timing and Switching Characteristics
      1. 8.18.1 Reset Timing
      2. 8.18.2 Wakeup Timing
      3. 8.18.3 Clock Specifications
        1. 8.18.3.1 48 MHz Crystal Oscillator (HFXT)
        2. 8.18.3.2 48 MHz RC Oscillator (HFOSC)
        3. 8.18.3.3 32 kHz Crystal Oscillator (LFXT)
        4. 8.18.3.4 32 kHz RC Oscillator (LFOSC)
    19. 8.19 Peripheral Characteristics
      1. 8.19.1 UART
        1. 8.19.1.1 UART Characteristics
      2. 8.19.2 SPI
        1. 8.19.2.1 SPI Characteristics
        2. 8.19.2.2 SPI Controller Mode
        3. 8.19.2.3 SPI Timing Diagrams - Controller Mode
        4. 8.19.2.4 SPI Peripheral Mode
        5. 8.19.2.5 SPI Timing Diagrams - Peripheral Mode
      3. 8.19.3 I2C
        1. 8.19.3.1 I2C
        2. 8.19.3.2 I2C Timing Diagram
      4. 8.19.4 GPIO
        1. 8.19.4.1 GPIO DC Characteristics
      5. 8.19.5 ADC
        1. 8.19.5.1 Analog-to-Digital Converter (ADC) Characteristics
      6. 8.19.6 Comparators
        1. 8.19.6.1 Ultra-low power comparator
  10. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  System CPU
    3. 9.3  Radio (RF Core)
      1. 9.3.1 Bluetooth 5.3 Low Energy
      2. 9.3.2 802.15.4 (Thread and Zigbee)
    4. 9.4  Memory
    5. 9.5  Cryptography
    6. 9.6  Timers
    7. 9.7  Serial Peripherals and I/O
    8. 9.8  Battery and Temperature Monitor
    9. 9.9  µDMA
    10. 9.10 Debug
    11. 9.11 Power Management
    12. 9.12 Clock Systems
    13. 9.13 Network Processor
  11. 10Application, Implementation, and Layout
    1. 10.1 Reference Designs
    2. 10.2 Junction Temperature Calculation
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
      1. 11.2.1 SimpleLink™ Microcontroller Platform
    3. 11.3 Documentation Support
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.9 µDMA

The device includes a direct memory access (µDMA) controller. The µDMA controller provides a way to offload data-transfer tasks from the system CPU, thus allowing for more efficient use of the processor and the available bus bandwidth. The µDMA controller can perform a transfer between memory and peripherals. The µDMA controller has dedicated channels for each supported on-chip module and can be programmed to automatically perform transfers between peripherals and memory when the peripheral is ready to transfer more data.

Some features of the µDMA controller include the following (this is not an exhaustive list):

  • Channel operation of up to 8 channels, with 6 channels having dedicated peripheral interface and 2 channels having ability to be triggered via configurable events.
  • Transfer modes: memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
    peripheral-to-peripheral
  • Data sizes of 8, 16, and 32 bits
  • Ping-pong mode for continuous streaming of data