SWRS272C april   2023  – june 2023 CC2340R5

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Revision History
  7. 6 Device Comparison
  8. 7 Pin Configuration and Functions
    1. 7.1 Pin Diagram – RKP Package (Top View)
    2. 7.2 Signal Descriptions – RKP Package
    3. 7.3 Connections for Unused Pins and Modules – RKP Package
    4. 7.4 Pin Diagram – RGE Package (Top View)
    5. 7.5 Signal Descriptions – RGE Package
    6. 7.6 Connections for Unused Pins and Modules – RGE Package
    7. 7.7 RKP and RGE Peripheral Pin Mapping
    8. 7.8 RKP and RGE Peripheral Signal Descriptions
  9. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  DCDC
    5. 8.5  Global LDO (GLDO)
    6. 8.6  Power Supply and Modules
    7. 8.7  Battery Monitor
    8. 8.8  Temperature Sensor
    9. 8.9  Power Consumption - Power Modes
    10. 8.10 Power Consumption - Radio Modes
    11. 8.11 Nonvolatile (Flash) Memory Characteristics
    12. 8.12 Thermal Resistance Characteristics
    13. 8.13 RF Frequency Bands
    14. 8.14 Bluetooth Low Energy - Receive (RX)
    15. 8.15 Bluetooth Low Energy - Transmit (TX)
    16. 8.16 Proprietary Radio Modes
    17. 8.17 2.4 GHz RX/TX CW
    18. 8.18 Timing and Switching Characteristics
      1. 8.18.1 Reset Timing
      2. 8.18.2 Wakeup Timing
      3. 8.18.3 Clock Specifications
        1. 8.18.3.1 48 MHz Crystal Oscillator (HFXT)
        2. 8.18.3.2 48 MHz RC Oscillator (HFOSC)
        3. 8.18.3.3 32 kHz Crystal Oscillator (LFXT)
        4. 8.18.3.4 32 kHz RC Oscillator (LFOSC)
    19. 8.19 Peripheral Characteristics
      1. 8.19.1 UART
        1. 8.19.1.1 UART Characteristics
      2. 8.19.2 SPI
        1. 8.19.2.1 SPI Characteristics
        2. 8.19.2.2 SPI Controller Mode
        3. 8.19.2.3 SPI Timing Diagrams - Controller Mode
        4. 8.19.2.4 SPI Peripheral Mode
        5. 8.19.2.5 SPI Timing Diagrams - Peripheral Mode
      3. 8.19.3 I2C
        1. 8.19.3.1 I2C
        2. 8.19.3.2 I2C Timing Diagram
      4. 8.19.4 GPIO
        1. 8.19.4.1 GPIO DC Characteristics
      5. 8.19.5 ADC
        1. 8.19.5.1 Analog-to-Digital Converter (ADC) Characteristics
      6. 8.19.6 Comparators
        1. 8.19.6.1 Ultra-low power comparator
  10. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  System CPU
    3. 9.3  Radio (RF Core)
      1. 9.3.1 Bluetooth 5.3 Low Energy
      2. 9.3.2 802.15.4 (Thread and Zigbee)
    4. 9.4  Memory
    5. 9.5  Cryptography
    6. 9.6  Timers
    7. 9.7  Serial Peripherals and I/O
    8. 9.8  Battery and Temperature Monitor
    9. 9.9  µDMA
    10. 9.10 Debug
    11. 9.11 Power Management
    12. 9.12 Clock Systems
    13. 9.13 Network Processor
  11. 10Application, Implementation, and Layout
    1. 10.1 Reference Designs
    2. 10.2 Junction Temperature Calculation
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
      1. 11.2.1 SimpleLink™ Microcontroller Platform
    3. 11.3 Documentation Support
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.11 Power Management

To minimize power consumption, the CC2340R5 supports a number of power modes and power management features (see Table 9-2).

Table 9-2 Power Modes
MODE SOFTWARE CONFIGURABLE POWER MODES (1) RESET PIN HELD
ACTIVE IDLE STANDBY SHUTDOWN
CPU Active Off Off Off Off
Flash On Available Off Off Off
SRAM On On Retention Off Off
Radio Available Available Off Off Off
Supply System On On Duty Cycled Off Off
CPU register retention Full Full Full (2) No No
SRAM retention Full Full Full Off Off
48 MHz high-speed clock (HFCLK) HFOSC (tracks HFXT) HFOSC (tracks HFXT) Off Off Off
32 kHz low-speed clock (LFCLK) LFXT or LFOSC LFXT or LFOSC LFXT or LFOSC Off Off
Peripherals Available Available IOC, BATMON, RTC, LPCOMP Off Off
Wake-up on RTC N/A Available Available Off Off
Wake-up on pin edge N/A Available Available Available Off
Wake-up on reset pin On On On On On
Brownout detector (BOD) On On Duty Cycled Off Off
Power-on reset (POR) On On On On On
Watchdog timer (WDT) Available Available Available Off Off
(1) “Available” indicates that the specific IP or feature can be enabled by user application in the corresponding device operating modes. “On” indicates that the specific IP or feature is turned on irrespective of the user application configuration of the device in the corresponding device operating mode. “Off” indicates that the specific IP or feature is turned off and not available for the user application in the corresponding device operating mode.
(2) Software-based retention of CPU registers with context save and restore when entering and exiting standby power mode

In the Active mode, both of MCU and AON power domains are powered. Clock gating is used to minimize power consumption. Clock gating to peripherals/subsystems is controlled manually by the CPU..

In Idle mode the CPU is in sleep but selected peripherals and subsystems (such as the radio) can be active. Infrastructure (Flash, ROM, SRAM, bus) clock gating is possible depending on state of the DMA and debug subsystem.

In Standby mode, only the always-on (AON) domain is active. An external wake-up event, RTC event, or comparator event (LP-COMP) is required to bring the device back to active mode. Pin Reset will also drive the device from Standby to Active. MCU peripherals with retention do not need to be reconfigured when waking up again, and the CPU continues execution from where it went into standby mode. All GPIOs are latched in standby mode.

In Shutdown mode, the device is entirely turned off (including the AON domain), and the I/Os are latched with the value they had before entering shutdown mode. A change of state on any I/O pin defined as a wake from shutdown pin wakes up the device and functions as a reset trigger. The CPU can differentiate between reset in this way and reset-by-reset pin or power-on reset, or thermal shutdown reset, by reading the reset status register. The only state retained in this mode are the latched I/O state, 3V register bank, and the flash memory contents.

Note:

The power, RF and clock management for the CC2340R5 device require specific configuration and handling by software for optimized performance. This configuration and handling is implemented in the TI-provided drivers that are part of the CC2340R5 software development kit (SDK). Therefore, TI highly recommends using this software framework for all application development on the device. The complete SDK with FreeRTOS, device drivers, and examples are offered free of charge in source code.