SWRS215D April   2019  – May 2021 CC3235S , CC3235SF

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Functional Block Diagrams
  5. Revision History
  6. Device Comparison
    1. 6.1 Related Products
  7. Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Pin Attributes
      1.     
    3. 7.3 Signal Descriptions
      1.     
    4. 7.4 Pin Multiplexing
    5. 7.5 Drive Strength and Reset States for Analog and Digital Multiplexed Pins
    6. 7.6 Pad State After Application of Power to Device, Before Reset Release
    7. 7.7 Connections for Unused Pins
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Power-On Hours (POH)
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Current Consumption Summary (CC3235S)
      1.     
      2.     
    6. 8.6  Current Consumption Summary (CC3235SF)
      1.     
      2.     
    7. 8.7  TX Power Control for 2.4 GHz Band
    8. 8.8  TX Power Control for 5 GHz
    9. 8.9  Brownout and Blackout Conditions
    10. 8.10 Electrical Characteristics for GPIO Pins
      1.     
      2.     
    11. 8.11 Electrical Characteristics for Pin Internal Pullup and Pulldown
    12. 8.12 WLAN Receiver Characteristics
      1.     
      2.     
    13. 8.13 WLAN Transmitter Characteristics
      1.     
      2.     
    14. 8.14 WLAN Transmitter Out-of-Band Emissions
      1.     
      2.     
    15. 8.15 BLE/2.4 GHz Radio Coexistence and WLAN Coexistence Requirements
    16. 8.16 Thermal Resistance Characteristics for RGK Package
    17. 8.17 Timing and Switching Characteristics
      1. 8.17.1 Power Supply Sequencing
      2. 8.17.2 Device Reset
      3. 8.17.3 Reset Timing
        1. 8.17.3.1 nRESET (32-kHz Crystal)
        2.      
        3.      
        4. 8.17.3.2 nRESET (External 32-kHz Clock)
          1.       
      4. 8.17.4 Wakeup From HIBERNATE Mode
      5. 8.17.5 Clock Specifications
        1. 8.17.5.1 Slow Clock Using Internal Oscillator
        2. 8.17.5.2 Slow Clock Using an External Clock
          1.       
        3. 8.17.5.3 Fast Clock (Fref) Using an External Crystal
          1.       
        4. 8.17.5.4 Fast Clock (Fref) Using an External Oscillator
          1.       
      6. 8.17.6 Peripherals Timing
        1. 8.17.6.1  SPI
          1. 8.17.6.1.1 SPI Master
            1.        
          2. 8.17.6.1.2 SPI Slave
            1.        
        2. 8.17.6.2  I2S
          1. 8.17.6.2.1 I2S Transmit Mode
            1.        
          2. 8.17.6.2.2 I2S Receive Mode
            1.        
        3. 8.17.6.3  GPIOs
          1. 8.17.6.3.1 GPIO Output Transition Time Parameters (Vsupply = 3.3 V)
            1.        
          2. 8.17.6.3.2 GPIO Input Transition Time Parameters
            1.        
        4. 8.17.6.4  I2C
          1.       
        5. 8.17.6.5  IEEE 1149.1 JTAG
          1.       
        6. 8.17.6.6  ADC
          1.       
        7. 8.17.6.7  Camera Parallel Port
          1.       
        8. 8.17.6.8  UART
        9. 8.17.6.9  SD Host
        10. 8.17.6.10 Timers
  9. Detailed Description
    1. 9.1  Overview
    2. 9.2  Arm® Cortex®-M4 Processor Core Subsystem
    3. 9.3  Wi-Fi® Network Processor Subsystem
      1. 9.3.1 WLAN
      2. 9.3.2 Network Stack
    4. 9.4  Security
    5. 9.5  FIPS 140-2 Level 1 Certification
    6. 9.6  Power-Management Subsystem
    7. 9.7  Low-Power Operating Mode
    8. 9.8  Memory
      1. 9.8.1 External Memory Requirements
      2. 9.8.2 Internal Memory
        1. 9.8.2.1 SRAM
        2. 9.8.2.2 ROM
        3. 9.8.2.3 Flash Memory
        4. 9.8.2.4 Memory Map
    9. 9.9  Restoring Factory Default Configuration
    10. 9.10 Boot Modes
      1. 9.10.1 Boot Mode List
    11. 9.11 Hostless Mode
  10. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
      1. 10.1.1 BLE/2.4 GHz Radio Coexistence
      2. 10.1.2 Antenna Selection
      3. 10.1.3 Typical Application
    2. 10.2 PCB Layout Guidelines
      1. 10.2.1 General PCB Guidelines
      2. 10.2.2 Power Layout and Routing
        1. 10.2.2.1 Design Considerations
      3. 10.2.3 Clock Interface Guidelines
      4. 10.2.4 Digital Input and Output Guidelines
      5. 10.2.5 RF Interface Guidelines
  11. 11Device and Documentation Support
    1. 11.1  Third-Party Products Disclaimer
    2. 11.2  Tools and Software
    3. 11.3  Firmware Updates
    4. 11.4  Device Nomenclature
    5. 11.5  Documentation Support
    6. 11.6  Related Links
    7. 11.7  Support Resources
    8. 11.8  Trademarks
    9. 11.9  Electrostatic Discharge Caution
    10. 11.10 Export Control Notice
    11. 11.11 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information
      1. 12.1.1 Package Option Addendum
        1. 12.1.1.1 Packaging Information
        2. 12.1.1.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Multiplexing

Table 7-4 Pin Multiplexing
Register AddressRegister NamePinANALOG OR SPECIAL FUNCTIONDigital Function (XXX Field Encoding)(1)
JTAGHostless ModeBLE COEX012345678910111213
CC_COEX_SW_OUTCC_COEX_BLE_IN
0x4402 E0C8GPIO_PAD_
CONFIG_10
1YYYGPIO10I2C_
SCL
GT_
PWM06
SDCARD_
CLK
UART1_
TX
GT_
CCP01
0x4402 E0CCGPIO_PAD_
CONFIG_11
2Y(2)YGPIO11I2C_
SDA
GT_
PWM07
pXCLK (XVCLK)SDCARD_
CMD
UART1_
RX
GT_
CCP02
MCAFSX
0x4402 E0D0GPIO_PAD_
CONFIG_12
3YYYGPIO12McACLKpVS (VSYNC)I2C_
SCL
UART0_
TX
GT_
CCP03
0x4402 E0D4GPIO_PAD_
CONFIG_13
4YYYGPIO13pHS (HSYNC)I2C_
SDA
UART0_
RX
GT_
CCP04
0x4402 E0D8GPIO_PAD_
CONFIG_14
5YYYGPIO14pDATA8 (CAM_D4)I2C_
SCL
GSPI_
CLK
GT_
CCP05
0x4402 E0DCGPIO_PAD_
CONFIG_15
6YYYGPIO15pDATA9 (CAM_D5)I2C_
SDA
GSPI_
MISO
SDCARD_
DATA0
GT_
CCP06
0x4402 E0E0GPIO_PAD_
CONFIG_16
7YYYGPIO16pDATA10 (CAM_D6)UART1_
TX
GSPI_
MOSI
SDCARD_
CLK
GT_
CCP07
0x4402 E0E4GPIO_PAD_
CONFIG_17
8Y(2)YGPIO17pDATA11 (CAM_D7)UART1_
RX
GSPI_
CS
SDCARD_
CMD
0x4402 E0F8GPIO_PAD_
CONFIG_22
15YYYGPIO22GT_
CCP04
McAFSX
0x4402 E0FCGPIO_PAD_
CONFIG_23
16Muxed with JTAGGPIO23TDIUART1_
TX
I2C_
SCL
0x4402 E100GPIO_PAD_
CONFIG_24
17Muxed with JTAG TDOGPIO24TDOUART1_
RX
GT_
CCP06
PWM0McAFSXI2C_
SDA
0x4402 E140GPIO_PAD_
CONFIG_40
18Y(3)Y(3)Y(3)GPIO28
0x4402 E110GPIO_PAD_
CONFIG_28
19Muxed with JTAG or SWD and TCKTCKGT_
PWM03
0x4402 E114GPIO_PAD_
CONFIG_29
20Muxed with JTAG or SWD and TMSCGPIO29TMS
0x4402 E104GPIO_PAD_
CONFIG_25
21(4)Y(2)YGPIO25McAFSXGT_
PWM02
0x4402 E11CGPIO_PAD_
CONFIG_31
45(3)(5)YYYGPIO31UART1_
RX
McAXR0GSPI_
CLK
UART0_
RX
McAFSX
0x4402 E0A0GPIO_PAD_
CONFIG_0
50YYYGPIO0UART0_
RTS
McAXR0McAXR1GT_
CCP00
GSPI_
CS
UART1_
RTS
UART0_
CTS
0x4402 E120GPIO_PAD_
CONFIG_32
52Y(3)Y(3)Y(3)GPIO32McACLKMcAXR0UART0_
RTS
GSPI_
MOSI
0x4402 E118GPIO_PAD_
CONFIG_30
53-—Y(3)Y(3)Y(3)GPIO30McACLKMcAFSXGT_
CCP05
GSPI_
MISO
UART0_
TX
0x4402 E0A4GPIO_PAD_
CONFIG_1
55GPIO1UART0_
TX
pCLK (PIXCLK)UART1_
TX
GT_
CCP01
0x4402 E0A8GPIO_PAD_
CONFIG_2
57GPIO2UART0_
RX
UART1_
RX
GT_
CCP02
0x4402 E0ACGPIO_PAD_
CONFIG_3
58Y(2)YGPIO3pDATA7 (CAM_D3)UART1_
TX
0x4402 E0B0GPIO_PAD_
CONFIG_4
59Y(2)YGPIO4pDATA6 (CAM_D2)UART1_
RX
0x4402 E0B4GPIO_PAD_
CONFIG_5
60YYYGPIO5pDATA5 (CAM_D1)McAXR1GT_
CCP05
0x4402 E0B8GPIO_PAD_
CONFIG_6
61YYYGPIO6UART1_
CTS
pDATA4 (CAM_D0)UART0_
RTS
UART0_
CTS
GT_
CCP06
0x4402 E0BCGPIO_PAD_
CONFIG_7
62GPIO7UART1_
RTS
UART0_
RTS
UART0_
TX
McACLKX
0x4402 E0C0GPIO_PAD_
CONFIG_8
63YYYGPIO8SDCARD_
IRQ
McAFSXGT_
CCP06
0x4402 E0C4GPIO_PAD_
CONFIG_9
64-—YYYGPIO9GT_
PWM05
SDCARD_
DATA0
McAXR0GT_
CCP00
Pin mux encodings with (RD) denote the default encoding after reset release.
Output Only
LPDS retention unavailable.
This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
Pin 45 is used by an internal DC/DC (ANA2_DCDC). For CC3235S device, pin 45 can be used as GPIO_31 if a supply is provided on pin 47.