SNAS843C December   2024  – July 2025 CDC6C

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Environmental Compliance
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Device Output Configurations
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bulk Acoustic Wave (BAW)
      2. 8.3.2 Device Block-Level Description
      3. 8.3.3 Function Pin
      4. 8.3.4 Clock Output Interfacing and Termination
      5. 8.3.5 Temperature Stability
      6. 8.3.6 Mechanical Robustness
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Driving Multiple Loads With a Single CDC6Cx
      2. 9.1.2 CDC6Cx CISPR25 Radiated Emission Performance
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Providing Thermal Reliability
        2. 9.4.1.2 Recommended Solder Reflow Profile
      2. 9.4.2 Layout Examples
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information
    2. 12.2 Orderable Part Number Decoder

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DLX|4
  • DLF|4
  • DLE|4
  • DLY|4
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3 Power Supply Recommendations

For the best electrical performance of the CDC6Cx, TI recommends using a single 1µF power supply bypass capacitor. TI also recommends using component side mounting of the power supply bypass capacitors. 0201 or 0402 body size capacitors facilitate best signal routing. Keep the connections between the bypass capacitors and the power supply on the device as short as possible. Ground the other side of the capacitor using a low impedance connection to the ground plane.

VDD power-up ramp time is defined as minimum time taken for power supply to exceed 95% of nominal VDD. Monotonic power supply ramp is assumed. In case the power supply falls between 1V to 1.5V after the power supply already reached >1.5V, the output is muted after power supply ramps back to >1.5V. The output clock recovers, when VDD is lowered below 1V and ramped back to >1.5V.