SNAS843C December   2024  – July 2025 CDC6C

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Environmental Compliance
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Device Output Configurations
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bulk Acoustic Wave (BAW)
      2. 8.3.2 Device Block-Level Description
      3. 8.3.3 Function Pin
      4. 8.3.4 Clock Output Interfacing and Termination
      5. 8.3.5 Temperature Stability
      6. 8.3.6 Mechanical Robustness
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Driving Multiple Loads With a Single CDC6Cx
      2. 9.1.2 CDC6Cx CISPR25 Radiated Emission Performance
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Providing Thermal Reliability
        2. 9.4.1.2 Recommended Solder Reflow Profile
      2. 9.4.2 Layout Examples
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information
    2. 12.2 Orderable Part Number Decoder

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DLX|4
  • DLF|4
  • DLE|4
  • DLY|4
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2 Detailed Design Procedure

The CDC6Cx has an integrated LDO and has excellent PSRR performance as shown in the Section 6.6 table. See the CDC6CEVM User's Guide for the reference layout recommendation while designing with the CDC6Cx BAW oscillator.

To set the pin 1 function for the CDC6Cx, connect typical 10kΩ or smaller resistor to VDD for driving the OE pin High. The device has an internal pullup resistor > 100kΩ, therefore this pin can be left open if an external pullup resistor is not desired. For driving the OE pin to Low, use the typical 10kΩ or smaller resistor as a pulldown resistor.

For EMI reduction, the CDC6Cx has orderable options to reduce rise and fall times. For applications requiring lesser EMI, select the appropriate rise and fall time options and see the CDC6Cx CISPR25 Radiated Emission Performance Report for more EMI reduction strategies.

The CDC6Cx has four slow mode options other than the normal mode. Based on the desired rise and fall times, select the right slow mode option and load capacitance value between 2pF, 5pF, 10pF and 15pF. Table 9-1 has recommended slow mode options for various load capacitance. For example, with load capacitance 15pF, Slow Mode 4 option results in the slowest rise and fall times. You can also select Slow Mode 1, Slow Mode 2, or Slow Mode 3 with 15pF but the rise and fall times are faster. The values in Table 9-1 are obtained using a 25MHz CDC6Cx.

Table 9-1 Rise / Fall Time Options (25MHz Output)
SLOW MODE OPTIONLOAD CAPACITANCERISE / FALL TIME (ns) WITH SLOW MODE (TYP / MAX)RISE / FALL TIME (ns) WITH NORMAL MODE (TYP / MAX)
Slow Mode 12pF0.42 / 0.750.28 / 0.65
Slow Mode 25pF1.11 / 2.00.33 / 0.8
Slow Mode 310pF1.85 / 3.10.44 / 1.7
Slow Mode 415pF2.7 / 4.00.87 / 2.2