SNAS843C December   2024  – July 2025 CDC6C

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Environmental Compliance
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Device Output Configurations
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bulk Acoustic Wave (BAW)
      2. 8.3.2 Device Block-Level Description
      3. 8.3.3 Function Pin
      4. 8.3.4 Clock Output Interfacing and Termination
      5. 8.3.5 Temperature Stability
      6. 8.3.6 Mechanical Robustness
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Driving Multiple Loads With a Single CDC6Cx
      2. 9.1.2 CDC6Cx CISPR25 Radiated Emission Performance
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Providing Thermal Reliability
        2. 9.4.1.2 Recommended Solder Reflow Profile
      2. 9.4.2 Layout Examples
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information
    2. 12.2 Orderable Part Number Decoder

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DLX|4
  • DLF|4
  • DLE|4
  • DLY|4
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Electrical Characteristics

over the recommended operating conditions (VDD = 1.8V ± 10%, 2.5V ± 10%, 3.3V ± 10%; typical values are at 25°C unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Current Consumption Characteristics
IDD Device current consumption (excluding load current) –40℃ to 85℃, Fout = 20 MHz, Vdd = 1.8V±10% 4.22 6.7 mA
–40℃ to 85℃, Fout = 20 MHz, Vdd = 3.3V±10% 4.41 6.7 mA
–40℃ to 105℃, Fout = 20 MHz, Vdd = 1.8V±10% 4.22 7.3 mA
–40℃ to 105℃, Fout = 20 MHz, Vdd = 3.3V±10% 4.41 7.3 mA
IDD Device current consumption (excluding load current) –40℃ to 85℃, Fout = 25 MHz, Vdd = 1.8V±10% 4.32 6.8 mA
–40℃ to 85℃, Fout = 25 MHz, Vdd = 3.3V±10% 4.57 6.9 mA
–40℃ to 105℃, Fout = 25 MHz, Vdd = 1.8V±10% 4.32 7.4 mA
–40℃ to 105℃, Fout = 25 MHz, Vdd = 3.3V±10% 4.57 7.5 mA
IDD Device current consumption (excluding load current) –40℃ to 85℃, Fout = 50 MHz, Vdd = 1.8V±10% 4.84 7.1 mA
–40℃ to 85℃, Fout = 50 MHz, Vdd = 3.3V±10% 5.33 7.2 mA
–40℃ to 105℃, Fout = 50 MHz, Vdd = 1.8V±10% 4.84 7.6 mA
–40℃ to 105℃, Fout = 50 MHz, Vdd = 3.3V±10% 5.33 7.8 mA
IDD Device current consumption (excluding load current) –40℃ to 85℃, Fout = 100 MHz, Vdd = 1.8V±10% 5.86 7.6 mA
–40℃ to 85℃, Fout = 100 MHz, Vdd = 3.3V±10% 6.77 9.0 mA
–40℃ to 105℃, Fout = 100 MHz, Vdd = 1.8V±10% 5.86 8.2 mA
–40℃ to 105℃, Fout = 100 MHz, Vdd = 3.3V±10% 6.77 9.0 mA
IDD Device current consumption (excluding load current) –40℃ to 85℃, Fout = 150 MHz, Vdd = 1.8V±10% 7.14 9.5 mA
–40℃ to 85℃, Fout = 150 MHz, Vdd = 3.3V±10% 8.72 11.0 mA
–40℃ to 105℃, Fout = 150 MHz, Vdd = 1.8V±10% 7.14 9.5 mA
–40℃ to 105℃, Fout = 150 MHz, Vdd = 3.3V±10% 8.72 11.0 mA
IDD_stdby Device standby current –40℃ to 85℃, ST = GND, Vdd=1.8V±10% 1.5 µA
–40℃ to 85℃, ST = GND, Vdd=2.5V±10% 2 µA
–40℃ to 85℃, ST = GND, Vdd=3.3V±10% 2.7 µA
–40℃ to 105℃, ST = GND, Vdd=1.8V±10% 1.5 µA
–40℃ to 105℃, ST = GND, Vdd=2.5V±10% 2 µA
–40℃ to 105℃, ST = GND, Vdd=3.3V±10% 2.7 µA
IDD-OD Device current with output disabled –40℃ to 85℃, Fout = 25 MHz, Vdd = 1.8V±10% 3.75 6.4 mA
–40℃ to 85℃, Fout = 25 MHz, Vdd = 3.3V±10% 3.76 6.5 mA
–40℃ to 105℃, Fout = 25 MHz, Vdd = 1.8V±10% 3.75 7 mA
–40℃ to 105℃, Fout = 25 MHz, Vdd = 3.3V±10% 3.76 7.1 mA
Output Characteristics
Fout Output frequency 0.25 200 MHz
VOL Output low voltage IOL = 3.6mA, VDD = 1.8V 0.36 V
IOL = 5.0mA, VDD = 2.5V 0.5 V
IOL = 6.6mA, VDD = 3.3V 0.66 V
VOH Output high voltage IOH = 3.6mA, VDD = 1.8V VDD × 0.88 V
IOH = 5.0mA, VDD = 2.5V VDD × 0.85 V
IOH = 6.6mA, VDD = 3.3V VDD × 0.85 V
tR/tF Output rise/fall time 20% to 80% of VOH-VOL, CL = 2pF, normal mode, Fout = 25MHz 0.28 0.65 ns
tR/tF Output rise/fall time 20% to 80% of VOH-VOL, CL = 2pF, slow mode 1, Fout = 25MHz 0.42 0.75 ns
tR/tF Output rise/fall time 20% to 80% of VOH-VOL, CL = 5pF, normal mode, Fout = 25MHz 0.33 0.8 ns
tR/tF Output rise/fall time 20% to 80% of VOH-VOL, CL = 5pF, slow mode 2, Fout = 25MHz 1.11 2.0 ns
tR/tF Output rise/fall time 20% to 80% of VOH-VOL, CL = 10pF, normal mode, Fout = 25MHz 0.44 1.7 ns
tR/tF Output rise/fall time 20% to 80% of VOH-VOL, CL = 10pF, slow mode 3, Fout = 25MHz 1.85 3.1 ns
tR/tF Output rise/fall time 20% to 80% of VOH-VOL, CL = 15pF, normal mode, Fout = 25MHz 0.87 2.2 ns
tR/tF Output rise/fall time 20% to 80% of VOH-VOL, CL = 15pF, slow mode 4, Fout = 25MHz 2.7 4.0 ns
ODC Output duty cycle 45 50 55 %
PN-Floor Output phase noise floor (fOFFSET > 10MHz) Fout = 50MHz –155 dBc/Hz
CL Maximum capacitive load Fout < 50MHz 30 pF
CL Fout > 50MHz 15 pF
Rout-high Output impedance 37.5 50 62.5 Ω
Function Pin Characteristics (OE/ST)
VIL Input low voltage 0.6 V
VIH Input high voltage 1.3 V
IIL Input low current EN = GND –40 µA
IIH Input high current EN = VDD 40 µA
CIN Input capacitance(1) 2 pF
Frequency Tolerance
FT Total frequency stability For DLE, DLF, and DLX packages only. Inclusive of: solder shift, initial tolerance, variation over –40℃ to 105℃, variation over supply voltage range, and 10 years aging at 25℃. ±25 ppm
FT Total frequency stability For DLE, DLF, and DLX packages only. Inclusive of: solder shift, initial tolerance, variation over –40℃ to 105℃, variation over supply voltage range, and 1st year aging at 25℃. ±20 ppm
FT Total frequency stability For DLY package only. Inclusive of: solder shift, initial tolerance, variation over –40℃ to 105℃, variation over supply voltage range, and 10 years aging at 25℃. ±50 ppm
FT Total frequency stability For DLY package only. Inclusive of: solder shift, initial tolerance, variation over –40℃ to 105℃, variation over supply voltage range, and 1st year aging at 25℃. ±45 ppm
FT Total frequency stability For DLE, DLF, and DLX packages only. Inclusive of: solder shift, initial tolerance, variation over –40℃ to 85℃, variation over supply voltage range, and 10 years aging at 25℃. ±25 ppm
FT Total frequency stability For DLE, DLF, and DLX packages only. Inclusive of: solder shift, initial tolerance, variation over –40℃ to 85℃, variation over supply voltage range, and 1st year aging at 25℃. ±20 ppm
FT Total frequency stability For DLY package only. Inclusive of: solder shift, initial tolerance, variation over –40℃ to 85℃, variation over supply voltage range, and 10 years aging at 25℃. ±50 ppm
FT Total frequency stability For DLY package only. Inclusive of: solder shift, initial tolerance, variation over –40℃ to 85℃, variation over supply voltage range, and 1st year aging at 25℃. ±45 ppm
PSRR Characteristics
PSRR Spur induced by 50mV power supply ripple at 50MHz output, VDD = 2.5V/3.3V, no power supply decoupling capacitor Sine wave at 50kHz –80 dBc
Sine wave at 100kHz –75 dBc
Sine wave at 500kHz –63 dBc
Sine wave at 1MHz –59 dBc
Power-On Characteristics
tSTART_UP Start-up time Time elapsed from 0.95 × VDD until output is enabled and output is within specification. OE / ST = High; Tested with a power supply ramp time of 200µs 1.5 3 ms
tRESUME Chip resume time Time elapsed from ST = VIH until output is enabled and output is within specification 3 ms
tST-DIS Chip disable time Time elapsed from ST = VIL until chip is in standby mode; for Fout > 100 MHz 250 ns
tOE-EN Output enable time Time elapsed from OE = VIH until output is enabled and output is within specification; for Fout > 100MHz 250 ns
tOE-DIS Output disable Time Time elapsed from OE = VIL until output is disabled; for Fout > 100 MHz 250 ns
Clock Output Jitter
RJ Random phase jitter 10MHz ≤ Fout < 25MHz, integration BW: 12kHz - 5MHz, maximum temperature = 105°C 400 1000 fs
RJ Random phase jitter 25MHz ≤ Fout ≤ 200MHz, integration BW: 12kHz - 20MHz, maximum temperature = 105°C 400 1000 fs
SPN100k Spot phase noise at 1kHz offset Fout = 100MHz –86 dBc/Hz
SPN100k Spot phase noise at 10kHz offset Fout = 100MHz –120 dBc/Hz
SPN100k Spot phase noise at 100kHz offset Fout = 100MHz –138 dBc/Hz
SPN1M Spot phase noise at 1MHz offset Fout = 100MHz –143 dBc/Hz
RJITT,RMS RMS period jitter Fout ≥ 25MHz  3 ps
RJITT,PK Peak-peak period jitter Fout ≥ 25MHz 26 ps
(1) Proven by Design. Not characterised