SLVSM66 November 2026 DP83C8201F

ADVANCE INFORMATION

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

RHB|32

Thermal pad, mechanical data (Package|Pins)

Orderable Information

slvsm66_oa

8.8 DP83C8201Fx Registers

Table 8-82 lists the memory-mapped registers for the DP83C8201Fx registers. All register offset addresses not listed in Table 8-82 should be considered as reserved locations and the register contents should not be modified.

Table 8-82 DP83C8201FX Registers

Offset	Acronym	Register Name	Section
0h	BMCR Register	Basic Mode Control Register	Section 8.8.1
1h	BMSR Register	Basic Mode Status Register	Section 8.8.3
2h	PHYIDR1 Register	PHY Identifier Register #1	Section 8.8.5
3h	PHYIDR2 Register	PHY Identifier Register #2	Section 8.8.7
4h	ANAR Register	Auto-Negotiation Advertisement Register	Section 8.8.9
5h	ALNPAR Register	Auto-Negotiation Link Partner Ability Register	Section 8.8.11
6h	ANER Register	Auto-Negotiation Expansion Register	Section 8.8.13
7h	ANNPTR Register	Auto-Negotiation Next Page Register	Section 8.8.15
8h	ANLNPTR Register	Auto-Negotiation Link Partner Ability Next Page Register	Section 8.8.17
9h	CR1 Register	Control Register #1	Section 8.8.19
Ah	CR2 Register	Control Register #2	Section 8.8.21
Bh	CR3 Register	Control Register #3	Section 8.8.23
Dh	REGCR Register	Extended Register Control Register	Section 8.8.25
Eh	ADDAR Register	Extended Register Data Register	Section 8.8.27
Fh	FLDS Register	Fast Link Down Status Register	Section 8.8.29
10h	PHYSTS Register	PHY Status Register	Section 8.8.31
11h	PHYSCR Register	PHY Specific Control Register	Section 8.8.33
12h	MISR1 Register	MII Interrupt Status Register #1	Section 8.8.35
13h	MISR2 Register	MII Interrupt Status Register #2	Section 8.8.37
14h	FCSCR Register	False Carrier Sense Counter Register	Section 8.8.39
15h	RECR Register	Receive Error Count Register	Section 8.8.41
16h	BISCR Register	BIST Control Register	Section 8.8.43
17h	RCSR Register	RMII and Status Register	Section 8.8.45
18h	LEDCR Register	LED Control Register	Section 8.8.47
19h	PHYCR Register	PHY Control Register	Section 8.8.49
1Ah	10BTSCR Register	10Base-Te Status/Control Register	Section 8.8.51
1Bh	BICSR1 Register	BIST Control and Status Register #1	Section 8.8.53
1Ch	BICSR2 Register	BIST Control and Status Register #2	Section 8.8.55
1Eh	CDCR Register	Cable Diagnostic Control Register	Section 8.8.57
1Fh	PHYRCR Register	PHY Reset Control Register	Section 8.8.59
25h	MLEDCR Register	Multi-LED Control Register	Section 8.8.61
27h	COMPT Regsiter	Compliance Test Register	Section 8.8.63
2Ah	10M_CFG		Section 8.8.65
117h	FLD_CFG1		Section 8.8.67
131h	FLD_CFG2		Section 8.8.69
170h	CDSCR Register	Cable Diagnostic Specific Control Register	Section 8.8.71
171h	CDSCR2 Register	Cable Diagnostic Specific Control Register 2	Section 8.8.73
173h	CDSCR3 Register	Cable Diagnostic Specific Control Register 3	Section 8.8.75
175h	TDR_175 Register	TDR Control Register #1	Section 8.8.77
176h	TDR_176 Register	TDR Control Register #2	Section 8.8.79
177h	CDSCR4 Register	Cable Diagnostic Specific Control Register 4	Section 8.8.81
178h	TDR_178 Register	TDR Control Register #3	Section 8.8.83
180h	CDLRR1 Register	Cable Diagnostic Location Result Register #1	Section 8.8.85
181h	CDLRR2 Register	Cable Diagnostic Location Result Register #2	Section 8.8.87
182h	CDLRR3 Register	Cable Diagnostic Location Result Register #3	Section 8.8.89
183h	CDLRR4 Register	Cable Diagnostic Location Result Register #4	Section 8.8.91
184h	CDLRR5 Register	Cable Diagnostic Location Result Register #5	Section 8.8.93
185h	CDLAR1 Register	Cable Diagnostic Amplitude Result Register #1	Section 8.8.95
186h	CDLAR2 Register	Cable Diagnostic Amplitude Result Register #2	Section 8.8.97
187h	CDLAR3 Register	Cable Diagnostic Amplitude Result Register #3	Section 8.8.99
188h	CDLAR4 Register	Cable Diagnostic Amplitude Result Register #4	Section 8.8.101
189h	CDLAR5 Register	Cable Diagnostic Amplitude Result Register #5	Section 8.8.103
18Ah	CDLAR6 Register	Cable Diagnostic Amplitude Result Register #6	Section 8.8.105
218h	MSE_Val		Section 8.8.107
302h	IO_CFG1 Register	GPIO Pin configuration Register #1	Section 8.8.109
303h	LED0 GPIO register	LED0 Configuration register	Section 8.8.111
304h	LED1 GPIO register	LED1 configuration register	Section 8.8.113
305h	LED2 register	LED2 configuration register	Section 8.8.115
306h	LED3 register	LED3 configuration register	Section 8.8.117
308h	CLK_OUT_LED_STATUS register	CLK_OUT_LED_STATUS configuration Register #3	Section 8.8.119
30Bh	VOD_CFG1 Register	VoD Config Register #1	Section 8.8.121
30Ch	VOD_CFG2 Register	VoD Config Register #2	Section 8.8.123
30Eh	VOD_CFG3 Register	VoD Config Register #3	Section 8.8.125
404h	ANA_LD_PROG_SL Register	Line Driver Config Register	Section 8.8.127
40Dh	ANA_RX10BT_CTRL Register	Receive Configuration Register 10M	Section 8.8.129
456h	GENCFG Register	General Configuration Register	Section 8.8.131
460h	LEDCFG Register	LEDs Configuration Register #1	Section 8.8.133
461h	IOCTRL Register	IO MUX GPIO Control Register	Section 8.8.135
467h	SOR1 Register	Strap Latch-In Register #2	Section 8.8.137
468h	SOR2 Register	Strap Latch-In Register #2	Section 8.8.139
469h	LEDCFG2 Register	LEDs Configuration Register #2	Section 8.8.141
4A0h	RXFCFG1 Register	Receive Configuration Register #1	Section 8.8.143
4A1h	RXFS Register	Receive Status Register	Section 8.8.145
4A2h	RXFPMD1 Register	Receive Perfect Match Data Register #1	Section 8.8.147
4A3h	RXFPMD2 Register	Receive Perfect Match Data Register #2	Section 8.8.149
4A4h	RXFPMD3 Register	Receive Perfect Match Data Register #3	Section 8.8.151
4A5h	RXFSOP1 Register	Receive Secure-ON Password Register #1	Section 8.8.153
4A6h	RXFSOP2 Register	Receive Secure-ON Password Register #2	Section 8.8.155
4A7h	RXFSOP3 Register	Receive Secure-ON Password Register #3	Section 8.8.157

Complex bit access types are encoded to fit into small table cells. Table 8-83 shows the codes that are used for access types in this section.

Table 8-83 DP83C8201Fx Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
RC	R C	Read to Clear
RCH	R C H	Read to Clear Set or cleared by hardware
RH	R H	Read Set or cleared by hardware
Write Type
W	W	Write
W0C	W 0C	Write 0 to clear
W1S	W 1S	Write 1 to set
Reset or Default Value
-n		Value after reset or the default value

8.1 BMCR Register (Offset = 0h) [Reset = XX00h]

BMCR Register is shown in Table 8-84.

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Basic Mode Control Register

Table 8-84 BMCR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Reset	RH/W1S	0h	PHY Software Reset: Writing a 1 to this bit resets the PHY PCS registers. When the reset operation is completed,, this bit is cleared to 0 automatically. PHY Vendor Specific registers are not cleared. 0h = Normal Operation 1h = Initiate software Reset / Reset in Progress
14	MII Loopback	R/W	0h	MII Loopback: When MII loopback mode is activated, the transmitted data presented on MII TXD is looped back to MII RXD internally. Additionally set following additional bit BISCR 0x0016[4:0] = 0b00100 for 100Base-TX and BISCR 0x0016[4:0] = 00001b for 10Base-Te 0h = Normal Operation 1h = MII Loopback enabled
13	Speed Selection	RH/W	X	Speed Selection: When Auto-Negotiation is disabled (bit [12] = 0 in Register 0x0000), writing to this bit allows the port speed to be selected. 0h = 10Mbps 1h = 100Mbps
12	Auto-Negotiation Enable	RH/W	X	Auto-Negotiation Enable.The default value is determined by strap. 0h = Disable Auto-Negotiation - bits [8] and [13] determine the port speed and duplex mode 1h = Enable Auto-Negotiation - bits [8] and [13] of this register are ignored when this bit is set
11	IEEE Power Down	R/W	0h	Power Down: The PHY is powered down after this bit is set. Only register access is enabled during this power down condition. To control the power down mechanism, this bit is OR'ed with the input from the INT/PWDN_N (in ENHANCED mode) pin. When the active low INT/PWDN_N pin is asserted low, this bit is set. 0h = Normal Operation 1h = IEEE Power Down
10	Isolate	RH/W	X	Isolate. This field defaults to zero. 0h = Normal Operation 1h = Isolates the port from the MII with the exception of the serial management interface. Also disables 50MHz clock in RMII Leader
9	Restart Auto-Negotiation	RH/W1S	0h	Restart Auto-Negotiation: If Auto-Negotiation is disabled (bit [12] = 0), bit [9] is ignored. This bit is self-clearing and returns a value of 1 until Auto-Negotiation is initiated, whereupon this bit self clears. Operation of the Auto-Negotiation process is not affected by the management entity clearing this bit. 0h = Normal Operation 1h = Restarts Auto-Negotiation, Re-initiates the Auto-Negotiation process
8	Duplex Mode	RH/W	X	Duplex Mode: When Auto-Negotiation is disabled, writing to this bit allows the port Duplex capability to be selected. This field defaults to zero. 0h = Half-Duplex 1h = Full-Duplex
7	Collision Test	R/W	0h	Collision Test: When set, this bit causes the COL signal to be asserted in response to the assertion of TX_EN within 512 bit times. The COL signal is de-asserted within 4 bit times in response to the de-assertion to TX_EN. 0h = Normal Operation 1h = Enable COL Signal Test
6-0	RESERVED	R	0h	Reserved

8.2 BMSR Register (Offset = 1h) [Reset = 7849h]

BMSR Register is shown in Table 8-85.

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Basic Mode Status Register

Table 8-85 BMSR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	100Base-T4	R	0h	100Base-T4 Capable: This protocol is not available. Always reads as 0.
14	100Base-TX Full-Duplex	R	1h	100Base-TX Full-Duplex Capable: 0h = Device not able to perform Full-Duplex 100Base-TX 1h = Device able to perform Full-Duplex 100Base-TX
13	100Base-TX Half-Duplex	R	1h	100Base-TX Half-Duplex Capable: 0h = Device not able to perform Half-Duplex 100Base-TX 1h = Device able to perform Half-Duplex 100Base-TX
12	10Base-T Full-Duplex	R	1h	10Base-T Full-Duplex Capable: 0h = Device not able to perform Full-Duplex 10Base-T 1h = Device able to perform Full-Duplex 10Base-T
11	10Base-T Half-Duplex	R	1h	10Base-T Half-Duplex Capable: 0h = Device not able to perform Half-Duplex 10Base-T 1h = Device able to perform Half-Duplex 10Base-T
10-7	RESERVED	R	0h	Reserved
6	SMI Preamble Suppression	R	1h	Preamble Suppression Capable: If this bit is set to 1, 32-bits of preamble needed only once after reset, invalid opcode or invalid turnaround. The device requires minimum of 500ns gap between two transactions, followed by one positive edge of MDC and MDIO=1, before starting the next transaction. 0h = Device not able to perform management transaction with preambles suppressed 1h = Device able to perform management transaction with preamble suppressed
5	Auto-Negotiation Complete	RH	0h	Auto-Negotiation Complete: 0h = Auto Negotiation process not completed (either still in process, disabled or reset) 1h = Auto-Negotiation process completed
4	Remote Fault	RC	0h	Remote Fault: Far End Fault indication or notification from Link Partner of Remote Fault. This bit is cleared on read or reset. 0h = No remote fault condition detected 1h = Remote fault condition detected
3	Auto-Negotiation Ability	R	1h	Auto-Negotiation Ability: 0h = Device is not able to perform Auto-Negotiation 1h = Device is able to perform Auto-Negotiation
2	Link Status	RC	0h	Link Status: Last latched value is cleared on read 0h = Link not established 1h = Valid link established (for either 10Mbps or 100Mbps operation)
1	Jabber Detect	RH	0h	Jabber Detect. This bit only has meaning for 10Base-T operation. 0h = No jabber condition detected 1h = Jabber condition detected
0	Extended Capability	R	1h	Extended Capability: 0h = Basic register set capabilities only 1h = Extended register capabilities

8.3 PHYIDR1 Register (Offset = 2h) [Reset = 2000h]

PHYIDR1 Register is shown in Table 8-86.

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PHY Identifier Register #1

Table 8-86 PHYIDR1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Organizationally Unique Identifier Bits 21:6	R	2000h	PHY Identifier Register #1

8.4 PHYIDR2 Register (Offset = 3h) [Reset = A134h]

PHYIDR2 Register is shown in Table 8-87.

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PHY Identifier Register #2

Table 8-87 PHYIDR2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	Organizationally Unique Identifier Bits 5:0	R	28h	PHY Identifier Register #2
9-4	Model Number	R	13h	Vendor Model Number: The six bits of vendor model number are mapped from bits [9] to [4] 11h = Basic Mode 13h = ENHANCED Mode
3-0	Revision Number	R	4h	Model Revision Number: Four bits of the vendor model revision number are mapped from bits [3:0]. This field is incremented for all major device changes.

8.5 ANAR Register (Offset = 4h) [Reset = 0XX1h]

ANAR Register is shown in Table 8-88.

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Auto-Negotiation Advertisement Register

Table 8-88 ANAR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Next Page	R/W	0h	Next Page Indication: 0h = Next Page Transfer not desired 1h = Next Page Transfer desired
14	RESERVED	R	0h	Reserved
13	Remote Fault	R/W	0h	Remote Fault: 0h = No Remote Fault detected 1h = Advertises that this device has detected a Remote Fault. Please note the PHY does not support Remote Fault. This bit shall not be set by Application
12	RESERVED	R	0h	Reserved
11	Asymmetric Pause	R/W	0h	Asymmetric Pause Support For Full-Duplex Links: 0h = Do not advertise asymmetric pause ability 1h = Advertise asymmetric pause ability
10	Pause	R/W	0h	Pause Support for Full-Duplex Links: 0h = Do not advertise pause ability 1h = Advertise pause ability
9	100Base-T4	R	0h	100Base-T4 Support: 0h = Do not advertise 100Base-T4 ability 1h = Advertise 100Base-T4 ability
8	100Base-TX Full-Duplex	RH/W	X	100Base-TX Full-Duplex Support: Values does not matter in force-mode. This field defaults to one. 0h = Do not advertise 100Base-TX Full-Duplex ability 1h = Advertise 100Base-TX Full-Duplex ability
7	100Base-TX Half-Duplex	RH/W	X	100Base-TX Half-Duplex Support: Values does not matter in force-mode. This field defaults to one. 0h = Do not advertise 100Base-TX Half-Duplex ability 1h = Advertise 100Base-TX Half-Duplex ability
6	10Base-T Full-Duplex	RH/W	X	10Base-T Full-Duplex Support: Values does not matter in force-mode. This field defaults to one. 0h = Do not advertise 10Base-T Full-Duplex ability 1h = Advertise 10Base-T Full-Duplex ability
5	10Base-T Half-Duplex	RH/W	X	10Base-T Half-Duplex Support: Values does not matter in force-mode. The default is determined by strap. 0h = Do not advertise 10Base-T Half-Duplex ability 1h = Advertise 10Base-T Half-Duplex ability
4-0	Selector Field	R/W	1h	Protocol Selection Bits: Technology selector field (IEEE802.3u <00001>)

8.6 ALNPAR Register (Offset = 5h) [Reset = 0000h]

ALNPAR Register is shown in Table 8-89.

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Auto-Negotiation Link Partner Ability Register

Table 8-89 ALNPAR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Next Page	R	0h	Next Page Indication: 0h = Link partner does not desire Next Page Transfer 1h = Link partner desires Next Page Transfer
14	Acknowledge	R	0h	Acknowledge: 0h = Link partner does not acknowledge reception of link code word 1h = Link partner acknowledges reception of link code word
13	Remote Fault	R	0h	Remote Fault: 0h = Link partner does not advertise remote fault event detection 1h = Link partner advertises remote fault event detection
12	RESERVED	R	0h	Reserved
11	Asymmetric Pause	R	0h	Asymmetric Pause: 0h = Link partner does not advertise asymmetric pause ability 1h = Link partner advertises asymmetric pause ability
10	Pause	R	0h	Pause: 0h = Link partner does not advertise pause ability 1h = Link partner advertises pause ability
9	100Base-T4	R	0h	100Base-T4 Support: 0h = Link partner does not advertise 100Base-T4 ability 1h = Link partner advertises 100Base-T4 ability
8	100Base-TX Full-Duplex	R	0h	100Base-TX Full-Duplex Support: 0h = Link partner does not advertise 100Base-TX Full-Duplex ability 1h = Link partner advertises 100Base-TX Full-Duplex ability
7	100Base-TX Half-Duplex	R	0h	100Base-TX Half-Duplex Support: 0h = Link partner does not advertise 100Base-TX Half-Duplex ability 1h = Link partner advertises 100Base-TX Half-Duplex ability
6	10Base-T Full-Duplex	R	0h	10Base-T Full-Duplex Support: 0h = Link partner does not advertise 10Base-T Full-Duplex ability 1h = Link partner advertises 10Base-T Full-Duplex ability
5	10Base-T Half-Duplex	R	0h	10Base-T Half-Duplex Support: 0h = Link partner does not advertise 10Base-T Half-Duplex ability 1h = Link partner advertises 10Base-T Half-Duplex ability
4-0	Selector Field	R	0h	Protocol Selection Bits: Technology selector field (IEEE802.3 <00001>)

8.7 ANER Register (Offset = 6h) [Reset = 0004h]

ANER Register is shown in Table 8-90.

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Auto-Negotiation Expansion Register

Table 8-90 ANER Register Field Descriptions

Bit	Field	Type	Reset	Description
15-5	RESERVED	R	0h	Reserved
4	Parallel Detection Fault	RH	0h	Parallel Detection Fault: 0h = No fault detected 1h = A fault has been detected during the parallel detection process
3	Link Partner Next Page Able	R	0h	Link Partner Next Page Ability: 0h = Link partner is not able to exchange next pages 1h = Link partner is able to exchange next pages
2	Local Device Next Page Able	R	1h	Next Page Ability: 0h = Local device is not able to exchange next pages 1h = Local device is able to exchange next pages
1	Page Received	RH	0h	Link Code Word Page Received: 0h = A new page has not been received 1h = A new page has been received
0	Link Partner Auto-Negotiation Able	R	0h	Link Partner Auto-Negotiation Ability: 0h = Link partner does not support Auto-Negotiation 1h = Link partner supports Auto-Negotiation

8.8 ANNPTR Register (Offset = 7h) [Reset = 2001h]

ANNPTR Register is shown in Table 8-91.

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Auto-Negotiation Next Page Register

Table 8-91 ANNPTR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Next Page	R/W	0h	Next Page Indication: 0h = Do not advertise desire to send additional next pages 1h = Advertise desire to send additional next pages
14	RESERVED	R	0h	Reserved
13	Message Page	R/W	1h	Message Page: 0h = Current page is an unformatted page 1h = Current page is a message page
12	Acknowledge 2	R/W	0h	Acknowledge2 is used by the next page function to indicate that Local Device has the ability to comply with the message received. 0h = Cannot comply with message 1h = Complies with message
11	Toggle	R	0h	Toggle is used by the Arbiitration function within Auto-Negotiation to synchronize with the Link Parnter during Next Page exchange. This bit always takes the opposite value of the Toggle bit in the previously exchanged Link Code Word. 0h = Value of toggle bit in previously transmitted Link Code Word was 1 1h = Value of toggle bit in previously transmitted Link Code Word was 0
10-0	CODE	R/W	1h	This field represents the code field of the next page transmission. If the Message Page bit is set (bit [13] of this register), then the code is interpreted as a Message Page, as defined in annex 28C of IEEE 802.3u. Otherwise, the code is interperated as an Unformatted Page, and the interpretation is application specific. The default value of the CODE represents a Null Page as defined in Annex 28C of IEEE 802.3u.

8.9 ANLNPTR Register (Offset = 8h) [Reset = 0000h]

ANLNPTR Register is shown in Table 8-92.

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Auto-Negotiation Link Partner Ability Next Page Register

Table 8-92 ANLNPTR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Next Page	R	0h	Next Page Indication: 0h = Do not advertise desire to send additional next pages 1h = Advertise desire to send additional next pages
14	Acknowledge	R	0h	Acknowledge: 0h = Link partner does not acknowledge reception of link code work 1h = Link partner acknowledges reception of link code word
13	Message Page	R	0h	Message Page: 0h = Current page is an unformatted page 1h = Current page is a message page
12	Acknowledge 2	R	0h	Acknowledge2 is used by the next page function to indicate that Local Device has the ability to comply with the message received. 0h = Cannot comply with message 1h = Complies with message
11	Toggle	R	0h	Toggle is used by the Arbiitration function within Auto-Negotiation to synchronize with the Link Parnter during Next Page exchange. This bit always takes the opposite value of the Toggle bit in the previously exchanged Link Code Word. 0h = Value of toggle bit in previously transmitted Link Code Word was 1 1h = Value of toggle bit in previously transmitted Link Code Word was 0
10-0	Message/Unformatted Field	R	0h	This field represents the code field of the next page transmission. If the Message Page bit is set (bit 13 of this register), then the code is interpreted as a Message Page, as defined in annex 28C of IEEE 802.3u. Otherwise, the code is interperated as an Unformatted Page, and the interpretation is application specific. The default value of the CODE represents a Null Page as defined in Annex 28C of IEEE 802.3u.

8.10 CR1 Register (Offset = 9h) [Reset = 00X0h]

CR1 Register is shown in Table 8-93.

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Control Register #1

Table 8-93 CR1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h	Reserved
9	RESERVED	R/W	0h	Reserved
8	TDR Auto-Run	R/W	0h	TDR Auto-Run at Link Down 0h = Disable automatic execution of TDR 1h = Enable execution of TDR procedure after link down event
7	Link Loss Recovery	R/W	0h	Link Loss Recovery: 0h = Normal Link Loss operation This mode allows recovery from short interference and continue to hold the link up for a few additional ms until the short interference is gone and the signal is OK. Under Normal Link Loss operation, Link status goes down approximately 250µs from signal loss. 1h = Enable Link Loss Recovery mechanism
6	RESERVED	R/W	0h	Reserved
5	Robust Auto MDIX	RH/W	X	Robust Auto-MDIX: If link partners are configured for operational modes that are not supported by normal Auto-MDIX, Robust Auto-MDIX allows MDI/MDIX resolution and prevents deadlock. When using in Force Mode, Robust Auto-MDIX shall be enabled. In BASIC mode, this field defaults to zero. In ENHANCED mode, the default is determined by strap. 0h = Disable Auto-MDIX 1h = Enable Robust Auto-MDIX
4	RESERVED	R/W	0h	Reserved
3-2	RESERVED	R/W	0h	Reserved
1	Fast RXDV Detection	R/W	0h	Fast RXDV Detection: 0h = Disable Fast RX_DV detection. The PHY operates in normal mode. RX_DV assertion after detection of /JK/. 1h = Enable assertion high of RX_DV on receive packet due to detection of /J/ symbol only. If a consecutive /K/ does not appear, RX_ER is generated.
0	RESERVED	R	0h	Reserved

8.11 CR2 Register (Offset = Ah) [Reset = 010Xh]

CR2 Register is shown in Table 8-94.

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Control Register #2

Table 8-94 CR2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R/W	0h	Reserved
14	RESERVED	R/W	0h	Reserved
13-7	RESERVED	R/W	0h	Reserved
6	RESERVED	R/W	0h	Reserved
5	Extended Full-Duplex Ability	R/W	0h	Extended Full-Duplex Ability: 0h = Disable Extended Full-Duplex Ability. Decision to work in Full-Duplex or Half-Duplex mode follows IEEE specification 1h = Enable Full-Duplex while working with link partner in force 100Base-TX. When the PHY is set to Auto-Negotiation or Force 100Base-TX and the link partner is operated in Force 100Base-TX, the link is always Full-Duplex
4	RESERVED	R/W	0h	Reserved
3	RESERVED	R/W	0h	Reserved
2	RX_ER During IDLE	R/W	0h	Detection of Receive Symbol Error During IDLE State: 0h = Disable detection of Receive symbol error during IDLE state 1h = Enable detection of Receive symbol error during IDLE state
1	Odd-Nibble Detection Disable	RH/W	X	Detection of Transmit Error. The default determined by strap. 0h = Enable detection of de-assertion of TX_EN on an odd-nibble boundary. In this case TX_EN is extended by one additional TX_CLK cycle and behaves as if TX_ER were asserted during that additional cycle 1h = Disable detection of transmit error in odd-nibble boundary
0	RESERVED	R/W	0h	Reserved

8.12 CR3 Register (Offset = Bh) [Reset = 0X00h]

CR3 Register is shown in Table 8-95.

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Control Register #3

Table 8-95 CR3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-11	RESERVED	R/W	0h	Reserved
10	FLD Descrambler Loss	RH/W	X	Descrambler Fast Link Drop: This option can be enabled in parallel to the other fast link down modes in bits [3:0]. The default is determined by strap. 0h = Do not drop the link on descrambler link loss 1h = Drop the link on descrambler link loss
9	RESERVED	R	0h	Reserved
8	RESERVED	R/W	0h	Reserved
7	RESERVED	R/W	0h	Reserved
6	Polarity Swap	R/W	0h	Polarity Swap: Port Mirror Function: To enable port mirroring, set this bit and bit [5] high. 0h = Inverted polarity on both pairs: TD+ and TD-, RD+ and RD- 1h = Normal polarity
5	MDI/MDIX Swap	R/W	0h	MDI/MDIX Swap: Port Mirror Function: To enable port mirroring, set this bit and bit [6] high. 0h = Swap MDI pairs (Receive on TD pair, Transmit on RD pair) 1h = MDI pairs normal (Receive on RD pair, Transmit on TD pair)
4	RESERVED	R/W	0h	Reserved
3-0	Fast Link Down Mode	RH/W	0h	Fast Link Down Modes: Bit 3 Drop the link based on RX Error count of the MII interface. When a predefined number of 32 RX Error occurences in a 10us interval is reached, the link is dropped. Bit 2 Drop the link based on MLT3 Error count (Violation of the MLT3 coding in the DSP output). When a predefined number of 20 MLT3 Error occurences in 10µs interval is reached, the link is dropped. Bit 1 Drop the link based on Low SNR Threshold. When a predefined number of 20 Threshold crossing occurences in a 10µs interval is reached, the link is dropped. Bit 0 Drop the link based on Signal/Energy Loss indication. When the Energy detector indicates Energy Loss, the link is dropped. Typical reaction time is 10µs C : Bit 0 default is 0 NC+ MII: Bit 0 is taken from STRAP in ENHANCED mode NC + RMII: Bit 0 default is 0 The Fast Link Down function is an OR of all 5 options (bits [10] and [3:0]), the designer can enable any combination of these conditions.

8.13 REGCR Register (Offset = Dh) [Reset = 0000h]

REGCR Register is shown in Table 8-96.

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Table 8-96 REGCR Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	Extended Register Command	R/W	0h	Extended Register Command: 0h = Address 1h = Data, no post increment 2h = Data, post increment on read and write 3h = Data, post increment on write only
13-5	RESERVED	R	0h	Reserved
4-0	DEVAD	R/W	0h	Device Address: Bits [4:0] are the device address, DEVAD, that directs any accesses of ADDAR register (0x000E) to the appropriate MMD. Specifically, the PHY uses the vendor specific DEVAD [4:0] = '11111' for accesses to registers 0x04D1 and lower. For MMD3 access, the DEVAD[4:0] = '00011'. For MMD7 access, the DEVAD[4:0] = '00111'. All accesses through registers REGCR and ADDAR can use the DEVAD for either MMD, MMD3 or MMD7. Transactions with other DEVAD are ignored.

8.14 ADDAR Register (Offset = Eh) [Reset = 0000h]

ADDAR Register is shown in Table 8-97.

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Table 8-97 ADDAR Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Address/Data	R/W	0h	If REGCR register bits [15:14] = '00', holds the MMD DEVAD's address register, otherwise holds the MMD DEVAD's data.

8.15 FLDS Register (Offset = Fh) [Reset = 0000h]

FLDS Register is shown in Table 8-98.

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Table 8-98 FLDS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-9	RESERVED	R	0h	Reserved
8-4	Fast Link Down Status	RCH	0h	Fast Link Down Status: Status Registers that latch high each time a given Fast Link Down mode is activated and causes a link drop (assuming the modes were enabled) 1h = Signal/Energy Lost 2h = SNR Level 4h = MLT3 Errors 8h = RX Errors 10h = Descrambler Loss Sync
3-0	RESERVED	R	0h	Reserved

8.16 PHYSTS Register (Offset = 10h) [Reset = 0002h]

PHYSTS Register is shown in Table 8-99.

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Table 8-99 PHYSTS Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	MDI/MDIX Mode	RH	0h	MDI/MDIX Mode Status: 0h = MDI Pairs swapped (Receive on TD pair, Transmit on RD pair) 1h = MDI Pairs normal (Receive on RD pair, Transmit on TD pair)
13	Receive Error Latch	RC	0h	Receive Error Latch: This bit is cleared upon a read of the RECR register 0h = No receive error event has occurred 1h = Receive error event has occurred since last read of RXERCNT register (0x0015)
12	Polarity Status	RC	0h	Polarity Status: This bit is a duplication of bit [4] in the 10BTSCR register (0x001A). This bit is cleared upon a read of the 10BTSCR register, but not upon a read of the PHYSTS register. 0h = Inverted Polarity detected 1h = Correct Polarity detected
11	False Carrier Sense Latch	RC	0h	False Carrier Sense Latch: This bit is cleared upon a read of the FCSR register. 0h = No False Carrier event has occurred 1h = False Carrier even has occurred since last read of FCSCR register (0x0014)
10	Signal Detect	RC	0h	Signal Detect: Active high 100Base-TX unconditional Signal Detect indication from PMD
9	Descrambler Lock	RC	0h	Descrambler Lock: Active high 100Base-TX Descrambler Lock indication from PMD
8	Page Received	RC	0h	Link Code Word Page Received: This bit is a duplicate of Page Received (bit [1]) in the ANER register and this bit is cleared on read of the ANER register (0x0006). 0h = Link Code Word Page has not been received 1h = A new Link Code Word Page has been received
7	MII Interrupt	RC	0h	MII Interrupt Pending: Interrupt source can be determined by reading the MISR register (0x0012). Reading the MISR clears this interrupt bit indication. 0h = No interrupt pending 1h = Indicates that an internal interrupt is pending
6	Remote Fault	RCH	0h	Remote Fault: Cleared on read of BMSR register (0x0001) or by reset. 1h = Remote Fault condition detected. Fault criteria: notification from link partner of Remote Fault via Auto-Negotiation 0h = No Remote Fault condition detected
5	Jabber Detect	RC	0h	Jabber Detection: This bit is only for 10Mbps operation. This bit is a duplicate of the Jabber Detect bit in the BMSR register (0x0001) and is not be cleared upon a read of the PHYSTS register. 0h = No Jabber 1h = Jabber condition detected
4	Auto-Negotiation Status	R	0h	Auto-Negotiation Status: 0h = Auto-Negotiation not complete 1h = Auto-Negotiation complete
3	MII Loopback Status	R	0h	MII Loopback Status: 0h = Normal operation 1h = Loopback enabled
2	Duplex Status	RH	0h	Duplex Status: 1 when Auto-Negotiation is disabled 0h = Half-Duplex mode 1h = Full-Duplex mode
1	Speed Status	RH	1h	Speed Status: 1 when Auto-Negotiation is disabled 0h = 100Mbps mode 1h = 10Mbps mode
0	Link Status	R	0h	Link Status: This bit is duplicated from the Link Status bit in the BMSR register ( address 0x0001) and is not be cleared upon a read of the PHYSTS register. 0h = No link established 1h = Valid link established (for either 10Mbps or 100Mbps)

8.17 PHYSCR Register (Offset = 11h) [Reset = 010Xh]

PHYSCR Register is shown in Table 8-100.

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Table 8-100 PHYSCR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Disable PLL	R/W	0h	Disable PLL: Note: clock circuitry can be disabled only in IEEE power down mode. 0h = Normal operation 1h = Disable internal clocks circuitry
14	Power Save Mode Enable	R/W	0h	Power Save Mode Enable: 0h = Normal operation 1h = Enable power save modes
13-12	Power Save Modes	R/W	0h	Power Save Mode: 0h = Normal operation mode. PHY is fully functional 1h = Reserved 2h = Active Sleep, Low Power Active Energy Saving mode that shuts down all internal circuitry besides SMI and energy detect functionalities. In this mode the PHY sends NLP every 1.4 seconds to wake up link partner. Automatic power-up is done when link partner is detected.
11	Scrambler Bypass	R/W	0h	Scrambler Bypass: 0h = Scrambler bypass disabled 1h = Scrambler bypass enabled
10	RESERVED	R/W	0h	Reserved
9-8	Loopback FIFO Depth	R/W	1h	Far-End Loopback FIFO Depth: This FIFO is used to adjust RX (receive) clock rate to TX clock rate. FIFO depth needs to be set based on expected maximum packet size and clock accuracy. Default value sets to 5 nibbles. 0h = 4 nibbles FIFO 1h = 5 nibbles FIFO 2h = 6 nibbles FIFO 3h = 8 nibbles FIFO
7-5	RESERVED	R	0h	Reserved
4	COL Full-Duplex Enable	R/W	0h	Collision in Full-Duplex Mode: 0h = Disable Collision in Full-Duplex mode. Collision remain active in Half-Duplex only. 1h = Enable generating Collision signaling in Full-Duplex mode
3	Interrupt Polarity	R/W	1h	Interrupt Polarity: 0h = Steady state (normal operation) is 0 logic and during interrupt is 1 logic 1h = Steady state (normal operation) is 1 logic and during interrupt is 0 logic
2	Test Interrupt	R/W	0h	Test Interrupt: Forces the PHY to generate an interrupt to facilitate interrupt testing. Interrupts continue to be generated as long as this bit remains set. 0h = Do not generate interrupt 1h = Generate an interrupt
1	Interrupt Enable	RH/W	X	Interrupt Enable: Enable interrupt dependent on the event enables in the MISR register (0x0012). 0h = Disable event based interrupts (default). 1h = Enable event based interrupts.
0	Interrupt Output Enable	RH/W	X	Interrupt Output Enable: Enable active low interrupt events as output via the INT pin 0h = Disable INT pin as an interrupt output (default). 1h = Enable INT pin as an interrupt output.

8.18 MISR1 Register (Offset = 12h) [Reset = 0000h]

MISR1 Register is shown in Table 8-101.

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Table 8-101 MISR1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Link Quality Interrupt	RC	0h	Change of Link Quality Status Interrupt: 0h = Link quality is Good 1h = Change of link quality when link is ON
14	Energy Detect Interrupt	RC	0h	Change of Energy Detection Status Interrupt: 0h = No change of energy detected 1h = Change of energy detected
13	Link Status Changed Interrupt	RC	0h	Change of Link Status Interrupt: 0h = No change of link status 1h = Change of link status interrupt is pending
12	Speed Changed Interrupt	RC	0h	Change of Speed Status Interrupt: 0h = No change of speed status 1h = Change of speed status interrupt is pending
11	Duplex Mode Changed Interrupt	RC	0h	Change of Duplex Status Interrupt: 0h = No change of duplex status 1h = Change of duplex status interrupt is pending
10	Auto-Negotiation Completed Interrupt	RC	0h	Auto-Negotiation Complete Interrupt: 0h = No Auto-Negotiation complete event is pending 1h = Auto-Negotiation complete interrupt is pending
9	False Carrier Counter Half-Full Interrupt	RC	0h	False Carrier Counter Half-Full Interrupt: 0h = False Carrier half-full event is not pending 1h = False Carrier counter (Register FCSCR, address 0x0014) exceeds half-full interrupt is pending
8	Receive Error Counter Half-Full Interrupt	RC	0h	Receiver Error Counter Half-Full Interrupt: 0h = Receive Error half-full event is not pending 1h = Receive Error counter (Register RECR, address 0x0015) exceeds half-full interrupt is pending
7	Link Quality Interrupt Enable	R/W	0h	Enable interrupt on change of link quality
6	Energy Detect Interrupt Enable	R/W	0h	Enable interrupt on change of energy detection
5	Link Status Changed Enable	R/W	0h	Enable interrupt on change of link status
4	Speed Changed Interrupt Enable	R/W	0h	Enable Interrupt on change of speed status
3	Duplex Mode Changed Interrupt Enable	R/W	0h	Enable Interrupt on change of duplex status
2	Auto-Negotiation Completed Enable	R/W	0h	Enable Interrupt on Auto-negotiation complete event
1	False Carrier HF Enable	R/W	0h	Enable Interrupt on False Carrier Counter Register half-full event
0	Receive Error HF Enable	R/W	0h	Enable Interrupt on Receive Error Counter Register half-full event

8.19 MISR2 Register (Offset = 13h) [Reset = 0000h]

MISR2 Register is shown in Table 8-102.

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Table 8-102 MISR2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	EEE Error Interrupt	RC	0h	Energy Efficient Ethernet Error Interrupt: 0h = EEE error has not occurred 1h = EEE error has occurred
14	Auto-Negotiation Error Interrupt	RC	0h	Auto-Negotiation Error Interrupt: 0h = No Auto-Negotiation error even pending 1h = Auto-Negotiation error interrupt is pending
13	Page Received Interrupt	RC	0h	Page Receiver Interrupt: 0h = Page has not been received 1h = Page has been received
12	Loopback FIFO OF/UF Event Interrupt	RC	0h	Loopback FIFO Overflow/Underflow Event Interrupt: 0h = No FIFO Overflow/Underflow event pending 1h = FIFO Overflow/Underflow event interrupt pending
11	MDI Crossover Change Interrupt	RC	0h	MDI/MDIX Crossover Status Change Interrupt: 0h = MDI crossover status has not changed 1h = MDI crossover status changed interrupt is pending
10	Sleep Mode Interrupt	RC	0h	Sleep Mode Event Interrupt: 0h = No Sleep mode event pending 1h = Sleep mode event interrupt is pending
9	Inverted Polarity Interrupt / WoL Packet Received Interrupt	RC	0h	Inverted Polarity Interrupt / WoL Packet Received Interrupt: 0h = Inverted polarity event pending / No WoL packet received 1h = No Inverted Polarity interrupt pending / WoL packet was recieved
8	Jabber Detect Interrupt	RC	0h	Jabber Detect Event Interrupt: 0h = No Jabber detect event pending 1h = Jabber detect even interrupt pending
7	EEE Error Interrupt Enable	R/W	0h	Enable interrupt on EEE Error
6	Auto-Negotiation Error Interrupt Enable	R/W	0h	Enable Interrupt on Auto-Negotiation error event
5	Page Received Interrupt Enable	R/W	0h	Enable Interrupt on page receive event
4	Loopback FIFO OF/UF Enable	R/W	0h	Enable Interrupt on loopback FIFO Overflow/Underflow event
3	MDI Crossover Change Enable	R/W	0h	Enable Interrupt on change of MDI/X status
2	Sleep Mode Event Enable	R/W	0h	Enable Interrupt on sleep mode event
1	Polarity Changed / WoL Packet Enable	R/W	0h	Enable Interrupt on change of polarity status
0	Jabber Detect Enable	R/W	0h	Enable Interrupt on Jabber detection event

8.20 FCSCR Register (Offset = 14h) [Reset = 0000h]

FCSCR Register is shown in Table 8-103.

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Table 8-103 FCSCR Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0h	Reserved
7-0	False Carrier Event Counter	RC	0h	False Carrier Event Counter: This 8-bit counter increments on every false carrier event. This counter stops when the maximum count (FFh) is reached. When the counter exceeds half-full (7Fh), an interrupt event is generated. This register is cleared on read.

8.21 RECR Register (Offset = 15h) [Reset = 0000h]

RECR Register is shown in Table 8-104.

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Table 8-104 RECR Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Receive Error Counter	RC	0h	RX_ER Counter: When a valid carrier is presented (only while RXDV is set), and there is at least one occurrence of an invalid data symbol, this 16-bit counter increments for each receive error detected. The RX_ER counter does not count in MII loopback mode. The counter stops when the maximum count (FFh) is reached. When the counter exceeds half-full (7Fh), an interrupt is generated. This register is cleared on read.

8.22 BISCR Register (Offset = 16h) [Reset = 0100h]

BISCR Register is shown in Table 8-105.

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Table 8-105 BISCR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	BIST Error Counter Mode	R/W	0h	BIST Error Counter Mode: 0h = Single mode, when BIST Error Counter reaches the max value, PRBS checker stops counting. 1h = Continuous mode, when the BIST Error counter reaches the max value, a pulse is generated and the counter starts counting from zero again.
13	PRBS Checker Config	R/W	0h	PRBS Checker Config:bit[13:12] 0h = PRBS Generator and Checker both are disabled 1h = PRBS Generator Enabled, Trasnmit Single Packet with Constant Data as configured in register 0x001C. Checker is disabled 2h = PRBS Generation is disabled. PRBS Checker is Enabled 3h = PRBS Generator and Checker both enabled. PRBS Generating Continous Packets as configured in register 0x001C
12	Packet Generation Enable	R/W	0h	Packet Generation Enable:bit[13:12] 0h = PRBS Generator and Checker both are disabled 1h = PRBS Generator Enabled, Trasnmit Single Packet with Constant Data as configured in register 0x001C. Checker is disabled 2h = PRBS Generation is disabled. PRBS Checker is Enabled 3h = PRBS Generator and Checker both enabled. PRBS Generating Continous Packets as configured in register 0x001C
11	PRBS Checker Lock/Sync	RH	0h	PRBS Checker Lock/Sync Indication: 0h = PRBS checker is not locked 1h = PRBS checker is locked and synced on received bit stream
10	PRBS Checker Sync Loss	RH	0h	PRBS Checker Sync Loss Indication: 0h = PRBS checker has not lost sync 1h = PRBS checker has lost sync
9	Packet Generator Status	RH	0h	Packet Generation Status Indication: 0h = Packet Generator is off 1h = Packet Generator is active and generating packets
8	Power Mode	RH	1h	Sleep Mode Indication: 0h = Indicates that the PHY is in active sleep mode 1h = Indicates that the PHY is in normal power mode
7	RESERVED	R	0h	Reserved
6	Transmit in MII Loopback	R/W	0h	Transmit Data in MII Loopback Mode (valid only at 100Mbps) 0h = Data is not transmitted to the line in MII loopback 1h = Enable transmission of data from the MAC received on the TX pins to the line in parallel to the MII loopback to RX pins. This bit can be set only in MII Loopback mode - setting bit [14] in BMCR register (0x0000)
5	RESERVED	R	0h	Reserved
4-0	Loopback Mode	R/W	0h	Loopback Mode Select: The PHY provides several options for loopback that test and verify various functional blocks within the PHY. Enabling loopback mode allows in-circuit testing of the PHY's digital and analog data paths 1h = PCS Input Loopback (Use for 10Base-Te only) 2h = PCS Output Loopback 4h = Digital Loopback ( Use for 100Base-TX Only) Additional Register writes are required. 8h = Analog Loopback (requires 100Ω termination) 10h = Reverse Loopback

8.23 RCSR Register (Offset = 17h) [Reset = 00X1h]

RCSR Register is shown in Table 8-106.

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Table 8-106 RCSR Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9	RESERVED	R	0h	Reserved
8	RMII TX Clock Shift	R/W	0h	RMII TX Clock Shift: Applicable only in RMII Follower 0h = Transmit path internal clock shift is disabled 1h = Transmit path internal clock shift is enabled
7	RESERVED	R	X	Reserved
6	RESERVED	R/W	0h	Reserved
5	RESERVED	R	X	Reserved
4	RMII Revision Select	R/W	0h	RMII Revision Select: 0h = (RMII revision 1.2) CRS_DV toggles at the end of a packet to indicate de-assertion of CRS 1h = (RMII revision 1.0) CRS_DV remains asserted until final data is transferred. CRS_DV does not toggle at the end of a packet
3	RMII Overflow Status	RC	0h	RX FIFO Overflow Status: 0h = Overflow detected 1h = Normal
2	RMII Underflow Status	RC	0h	RX FIFO Underflow Status: 0h = Underflow detected 1h = Normal
1-0	Receive Elasticity Buffer Size	R/W	1h	Receive Elasticity Buffer Size: This field controls the Receive Elasticity Buffer which allows for frequency variation tolerance between the 50MHz RMII clock and the recovered data. The following values indicate the tolerance in bits for a single packet. The minimum setting allows for standard Ethernet frame sizes at +/-50ppm accuracy. For greater frequency tolerance, the packet lengths can be scaled (for +/-100ppm), divide the packet lengths by 2). 0h = 14 bit tolerance (up to 16800 byte packets) 1h = 2 bit tolerance (up to 2400 byte packets) 2h = 6 bit tolerance (up to 7200 byte packets) 3h = 10 bit tolerance (up to 12000 byte packets)

8.24 LEDCR Register (Offset = 18h) [Reset = 04X0h]

LEDCR Register is shown in Table 8-107.

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Table 8-107 LEDCR Register Field Descriptions

Bit	Field	Type	Reset	Description
15-11	RESERVED	R	0h	Reserved
10-9	Blink Rate	R/W	2h	LED Blinking Rate (ON/OFF duration): 0h = 20Hz (50ms) 1h = 10Hz (100ms) 2h = 5Hz (200ms) 3h = 2Hz (500ms)
8	RESERVED	R/W	0h	Reserved
7	LED Link Polarity	RH/W	X	LED Link Polarity Setting: Link LED polarity is Active Low in BASIC mode and defined by direction of strapping on this pin in ENHANCED mode. This register allows for override of this strap value. 0h = Active Low polarity setting 1h = Active High polarity setting
6-5	RESERVED	R/W	0h	Reserved
4	Drive Link LED	R/W	0h	Drive Link LED Select: 0h = Normal operation 1h = Drive value of ON/OFF bit [1] onto LED0 output pin
3-2	RESERVED	R/W	0h	Reserved
1	Link LED ON/OFF Setting	R/W	0h	Value to force on Link LED output 0h = LOW 1h = HIGH
0	RESERVED	R/W	0h	Reserved

8.25 PHYCR Register (Offset = 19h) [Reset = X0XXh]

PHYCR Register is shown in Table 8-108.

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Table 8-108 PHYCR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Auto MDI/X Enable	RH/W	X	Auto-MDIX Enable: In BASIC Mode, defaults to Auto-MDIX enabled. In ENHANCED mode, default determined by strap. 0h = Disable Auto-Negotiation Auto-MDIX capability 1h = Enable Auto-Negotiation Auto-MDIX capability
14	Force MDI/X	RH/W	X	Force MDIX: ENHANCED Mode: When Auto-MDIX strap is disabled, latched by FORCE MDI/MDIX strap 0h = Force MDI pairs to cross (Receive on TD pair, Transmit on RD pair) 1h = Normal operation (Receive on RD pair, Transmit on TD pair)
13	Pause RX Status	R	0h	Pause Receive Negotiation Status: Indicates that pause receive can be enabled in the MAC. Based on bits [11:10] in ANAR register and bits [11:10] in ANLPAR register settings. The function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, 'Pause Resolution', only if the Auto-Negotiation highest common denominator is a Full-Duplex technology.
12	Pause TX Status	R	0h	Pause Transmit Negotiated Status: Indicates that pause can be enabled in the MAC. Based on bits [11:10] in ANAR register and bits [11:10] in ANLPAR register settings. This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, 'Pause Resolution', only if the Auto-Negotiation highest common denominator is a Full-Duplex technology.
11	MII Link Status	R	0h	MII Link Status: 0h = No active 100Base-TX Full-Duplex link, established using Auto-Negotiation 1h = 100Base-TX Full-Duplex link is active and was established using Auto-Negotiation
10-8	RESERVED	R	0h	Reserved
7	Bypass LED Stretching	R/W	0h	Bypass LED Stretching: Set this bit to '1' to bypass the LED stretching, the LED reflects the internal value. 0h = Normal LED operation 1h = Bypass LED stretching
6	RESERVED	R/W	0h	Reserved
5	RESERVED	R/W	0h	Reserved
4-0	PHY Address	RH	X	PHY Address: In BASIC and ENHANCED mode, default determined by strap.

8.26 10BTSCR Register (Offset = 1Ah) [Reset = 0000h]

10BTSCR Register is shown in Table 8-109.

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Table 8-109 10BTSCR Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	RESERVED	R	0h	Reserved
13	Receiver Threshold Enable	R/W	0h	Lower Receiver Threshold Enable: 0h = Normal 10Base-T operation 1h = Enable 10Base-T lower receiver threshold to allow operation with longer cables
12-9	Squelch	R/W	0h	Squelch Configuration: Used to set the Peak Squelch 'ON' threshold for the 10Base-T receiver. Starting from 200mV to 600mV, step size of 50mV with some overlapping as shown below: 0h = 200mV 1h = 250mV 2h = 300mV 3h = 350mV 4h = 400mV 5h = 450mV 6h = 500mV 7h = 550mV 8h = 600mV
8	RESERVED	R/W	0h	Reserved
7	NLP Disable	R/W	0h	NLP Transmission Control: 0h = Enable transmission of NLPs 1h = Disable transmission of NLPs
6-5	RESERVED	R	0h	Reserved
4	Polarity Status	R	0h	Polarity Status: This bit is a duplication of bit [12] in the PHYSTS register (0x0010). Both bits are cleared upon a read of 10BTSCR register, but not upon a read of the PHYSTS register. 0h = Inverted Polarity detected 1h = Correct Polarity detected
3-1	RESERVED	R	0h	Reserved
0	Jabber Disable	R/W	0h	Jabber Disable: Note: This function is only applicable in 10Base-Te operation. 0h = Jabber function enabled 1h = Jabber function disabled

8.27 BICSR1 Register (Offset = 1Bh) [Reset = 007Dh]

BICSR1 Register is shown in Table 8-110.

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Table 8-110 BICSR1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	BIST Error Count	R	0h	BIST Error Count: Holds number of errored bytes received by the PRBS checker. Value in this register is locked and cleared when write is done to bit [15]. When BIST Error Counter Mode is set to '0', count stops on 0xFF (see register 0x0016) Note: Writing '1' to bit [15] locks the counter's value for successive read operation and clear the BIST Error Counter.
7-0	BIST IPG Length	R/W	7Dh	BIST IPG Length: Inter Packet Gap (IPG) Length defines the size of the gap (in bytes) between any 2 successive packets generated by the BIST. Default value is 0x7D (equal to 125 bytes*4 = 500 bytes). Binary values shall be multiplied by 4 to get the actual IPG length

8.28 BICSR2 Register (Offset = 1Ch) [Reset = 05EEh]

BICSR2 Register is shown in Table 8-111.

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Table 8-111 BICSR2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-11	RESERVED	R	0h	Reserved
10-0	BIST Packet Length	R/W	5EEh	BIST Packet Length: Length of the generated BIST packets. The value of this register defines the size (in bytes) of every packet that is generated by the BIST. Default value is 0x05EE, which is equal to 1518 bytes.

8.29 CDCR Register (Offset = 1Eh) [Reset = 0102h]

CDCR Register is shown in Table 8-112.

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Table 8-112 CDCR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Cable Diagnostic Start	R/W	0h	Cable Diagnostic Process Start: Diagnostic Start bit is cleared once Diagnostic Done indication bit is triggered. 0h = Cable Diagnostic is disabled 1h = Start cable measurement
14	cfg_rescal_en	R/W	0h	Resistor Calibration Start. This field should normally be low. If this field is ever read as high, a write shall be done to deassert this bit, immediately followed by a Hard Reset (Reg 0x1F[15])
13-2	RESERVED	R	0h	Reserved
1	Cable Diagnostic Status	RH	1h	Cable Diagnostic Process Done: 0h = Cable Diagnostic had not completed 1h = Indication that cable measurement process is complete
0	Cable Diagnostic Test Fail	RH	0h	Cable Diagnostic Process Fail: 0h = Cable Diagnostic has not failed 1h = Indication that cable measurement process failed

8.30 PHYRCR Register (Offset = 1Fh) [Reset = 0000h]

PHYRCR Register is shown in Table 8-113.

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Table 8-113 PHYRCR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Software Hard Reset	RH/W1S	0h	Software Hard Reset: 0h = Normal Operation 1h = Reset PHY. This bit is self cleared and has the same effect as Hardware reset pin.
14	Digital reset	RH/W1S	0h	Software Restart: 0h = Normal Operation 1h = Restart PHY. This bit is self cleared and resets all PHY circuitry except the registers.
13	RESERVED	R/W	0h	Reserved
12-0	RESERVED	R/W	0h	Reserved

8.31 MLEDCR Register (Offset = 25h) [Reset = 0041h]

MLEDCR Register is shown in Table 8-114.

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Table 8-114 MLEDCR Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R/W	0h	Reserved
9	MLED Polarity Swap	R/W	0h	MLED Polarity Swap: The polarity of MLED depends on the routing configuration and the strap on LED1 pin. If the pin strap is pull-up, then polarity is active low. If the pin strap is pull-down then polarity is active high.
8-7	RESERVED	R/W	0h	Reserved
6-3	LED0 Configuration	R/W	8h	MLED Configurations: Selects the source for LED0 0h = LINK OK 1h = RX/TX Activity 2h = TX Activity 3h = RX Activity 4h = Collision 5h = Speed, High for 100BASE-TX 6h = Speed, High for 10BASE-T 7h = Full-Duplex 8h = LINK OK / BLINK on TX/RX Activity 9h = Active Stretch Signal Ah = MII LINK (100BT+FD) Bh = LPI Mode (EEE) Ch = TX/RX MII Error Dh = Link Lost (remains on until register 0x0001 is read) Eh = Blink for PRBS error (remains ON for single error, remains until counter is cleared) Fh = Reserved
2-1	RESERVED	R	0h	Reserved
0	cfg_mled_en	R/W	1h	MLED Route to LED0: 0h = Reserved 1h = Value routed as per MLEDCR[6:3]

8.32 COMPT Regsiter Register (Offset = 27h) [Reset = 0000h]

COMPT Regsiter is shown in Table 8-115.

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Table 8-115 COMPT Regsiter Register Field Descriptions

Bit	Field	Type	Reset	Description
15-4	RESERVED	R/W	0h	Reserved
3-0	Compliance Test Configuration	R/W	0h	Compliance Test Configuration Select: Bit [4] in Register 0x0027 = 1, Enables 10Base-T Test Patterns Bit [4] in Register 0x0428 = 1, Enables 100Base-TX Test Modes Bits [3:0] select the 10Base-T test pattern, as follows: 0000 = Single NLP 0001 = Single Pulse 1 0010 = Single Pulse 0 0011 = Repetitive 1 0100 = Repetitive 0 0101 = Preamble (repetitive '10') 0110 = Single 1 followed by TP_IDLE 0111 = Single 0 followed by TP_IDLE 1000 = Repetitive '1001' sequence 1001 = Random 10Base-T data 1010 = TP_IDLE_00 1011 = TP_IDLE_01 1100 = TP_IDLE_10 1101 = TP_IDLE_11 100Base-TX Test Mode is determined by bits {[5] in register 0x0428, [3:0] in register 0x0027}. The bits determine the number of 0's to follow a '1'. 0,0001 = Single '0' after a '1' 0,0010 = Two '0' after a '1' 0,0011 = Three '0' after a '1' 0,0100 = Four '0' after a '1' 0,0101 = Five '0' after a '1' 0,0110 = Six '0' after a '1' 0,0111 = Seven '0' after a '1' ... 1,1111 = Thirty one '0' after a '1' 0,0000 = Clears the shift register Note 1: To reconfigure the 100Base-TX Test Mode, bit [4] must be cleared in register 0x0428 and then reset to '1' to configure the new pattern. Note 2: When performing 100Base-TX or 10Base-T tests modes, the speed must be force using the Basic Mode Control Register (BMCR), address 0x0000.

8.33 10M_CFG Register (Offset = 2Ah) [Reset = 7998h]

10M_CFG is shown in Table 8-116.

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Table 8-116 10M_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	10M Preamble Mode	R/W	1h	The device supports two preamble size for 10Mbps. - (0) Long Preamble Mode (1) Short Preamble Mode, This does not affect the 100Mbps mode. In Long Preamble mode, "Long" denotes the number of preamble received from MDI. In this mode, the receiver takes up to 7 bytes of preamble to declare this as a valid preamble. The preamble on the MAC can have lesser preambles than the bytes from MDI. The device expects at least 7 bytes of preamble to be on the MDI line. In Short Preamble mode, "Short" denotes the preamble bytes on the MDI line. In this mode, the receiver can work with shorter preambles > 3 bytes. If Link Partner is expected to transfer shorter preamble ( < 3 bytes), the recommendation is to configure to "Long" preamble mode. 0h = Long Preamble Mode 1h = Short Preamble Mode
13-0	RESERVED	R/W	0h	Reserved

8.34 FLD_CFG1 Register (Offset = 117h) [Reset = 8147h]

FLD_CFG1 is shown in Table 8-117.

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Table 8-117 FLD_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	Config MLT3 Error Cnt Len	R/W	20h	MLT3 Error count window. Sets the window in terns if number of clocks (8ns). The counter counts in steady state. 0h = Reserved 1h = 2 cycle 3Fh = 64 cycle
9-4	Config MLT3 Error Number Cnt	R/W	14h	Numbers of MLT3 errors to be counted for link down 0h = Reserved 1h = 1 Error 3Fh = 63 Errors
3-0	RESERVED	R	0h	Reserved

8.35 FLD_CFG2 Register (Offset = 131h) [Reset = 0288h]

FLD_CFG2 is shown in Table 8-118.

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Table 8-118 FLD_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-6	RESERVED	R/W	0h	Reserved
5-0	Config Scrambler Threshold	R/W	8h	Configures the window to declare link down based on descrambler errors.

8.36 CDSCR Register (Offset = 170h) [Reset = 0C12h]

CDSCR Register is shown in Table 8-119.

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Table 8-119 CDSCR Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	Cable Diagnostic Cross Disable	R/W	0h	Cross TDR Diagnostic Mode: 0h = TDR looks for reflections on channel other than the transmit channel configured by 0x170[13] 1h = TDR looks for reflections on same channel as transmit channel configured by 0x170[13]
13	cfg_tdr_chan_sel	R/W	0h	TDR TX channel select: 0h = Select channel A as transmit channel. 1h = Select channel B as transmit channel.
12	cfg_tdr_dc_rem_no_init	R/W	0h	To make sure DC removal module is not reset before TDR and dc removal is effective on TDR reflection
11	RESERVED	R/W	0h	Reserved
10-8	Cable Diagnostic Average Cycles	R/W	4h	Number of TDR Cycles to Average: 0h = 1 TDR cycle 1h = 2 TDR cycles 2h = 4 TDR cycles 3h = 8 TDR cycles 4h = 16 TDR cycles 5h = 32 TDR cycles 6h = 64 TDR cycles 7h = Reserved
7	RESERVED	R/W	0h	Reserved
6-4	cfg_tdr_seg_num	R/W	1h	Selects cable segment on which TDR is to be performed - 000b = Reserved 001b = 0m to 10m 010b = 10m to 20m 011b = 20m to 40m 100b = 40m to 80m 101b = 80m and beyond 110b = Reserved 111b = Reserved
3-0	RESERVED	R/W	0h	Reserved

8.37 CDSCR2 Register (Offset = 171h) [Reset = C850h]

CDSCR2 Register is shown in Table 8-120.

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Table 8-120 CDSCR2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	RESERVED	R/W	0h	Reserved

8.38 CDSCR3 Register (Offset = 173h) [Reset = 0D04h]

CDSCR3 Register is shown in Table 8-121.

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Table 8-121 CDSCR3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	cfg_tdr_seg_duration	R/W	Dh	Duration of the segment selected for TDR, calculated by - (Length_in_meters25.2)/8 For Segment #1, 8'hD For Segment #2, 8'hD For Segment #3, 8'h1A For Segment #4, 8'h34 For Segment #5, 8'h8F
7-0	cfg_tdr_initial_skip	R/W	4h	No of samples to be avoided before start of segment configured - For Segment #1, 8'h7 For Segment #2, 8'h14 For Segment #3, 8'h21 For Segment #4, 8'h3B For Segment #5, 8'h6F

8.39 TDR_175 Register (Offset = 175h) [Reset = 1004h]

TDR_175 Register is shown in Table 8-122.

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Table 8-122 TDR_175 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	RESERVED	R	0h	Reserved
13-11	cfg_tdr_sdw_avg_loc	R/W	2h	TDR shadow average location - For Segment #1, 3'h2 For Segment #2, 3'h2 For Segment #3, 3'h2 For Segment #4, 3'h2 For Segment #5, 3'h2
10-5	RESERVED	R	0h	Reserved
4	RESERVED	R/W	0h	Reserved
3-0	cfg_tdr_fwd_shadow	R/W	4h	Length of forward shadow for the segment configured (to avoid shadow of a fault peak be seen as another fault peak) - For Segment #1, 4'h4 For Segment #2, 4'h4 For Segment #3, 4'h5 For Segment #4, 4'h8 For Segment #5, 4'hB

8.40 TDR_176 Register (Offset = 176h) [Reset = 0005h]

TDR_176 Register is shown in Table 8-123.

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Table 8-123 TDR_176 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-5	RESERVED	R	0h	Reserved
4-0	cfg_tdr_p_loc_thresh_seg	R/W	5h

8.41 CDSCR4 Register (Offset = 177h) [Reset = 1E00h]

CDSCR4 Register is shown in Table 8-124.

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Table 8-124 CDSCR4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	RESERVED	R/W	0h	Reserved
12-8	Short Cables Threshold	R/W	1Eh	TH to compensate for strong reflections in short cables
7-0	RESERVED	R/W	0h	Reserved

8.42 TDR_178 Register (Offset = 178h) [Reset = 0002h]

TDR_178 Register is shown in Table 8-125.

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Table 8-125 TDR_178 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-3	RESERVED	R	0h	Reserved
2-0	cfg_tdr_tx_pulse_width_seg	R/W	2h	TDR TX Pulse width for Segment - For Segment #1, 3'h2 For Segment #2, 3'h2 For Segment #3, 3'h2 For Segment #4, 3'h2 For Segment #5, 3'h6

8.43 CDLRR1 Register (Offset = 180h) [Reset = 0000h]

CDLRR1 Register is shown in Table 8-126.

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Table 8-126 CDLRR1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0h	Reserved
7-0	TD Peak Location 1	R	0h	Location of the First peak discovered by the TDR mechanism on Transmit Channel (TD). The value of these bits need to be translated into distance from the PHY.

8.44 CDLRR2 Register (Offset = 181h) [Reset = 0000h]

CDLRR2 Register is shown in Table 8-127.

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Table 8-127 CDLRR2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	RESERVED	R	0h	Reserved

8.45 CDLRR3 Register (Offset = 182h) [Reset = 0000h]

CDLRR3 Register is shown in Table 8-128.

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Table 8-128 CDLRR3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	RESERVED	R	0h	Reserved

8.46 CDLRR4 Register (Offset = 183h) [Reset = 0000h]

CDLRR4 Register is shown in Table 8-129.

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Table 8-129 CDLRR4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	RESERVED	R	0h	Reserved

8.47 CDLRR5 Register (Offset = 184h) [Reset = 0000h]

CDLRR5 Register is shown in Table 8-130.

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Table 8-130 CDLRR5 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	RESERVED	R	0h	Reserved

8.48 CDLAR1 Register (Offset = 185h) [Reset = 0000h]

CDLAR1 Register is shown in Table 8-131.

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Table 8-131 CDLAR1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-7	RESERVED	R	0h	Reserved
6-0	TD Peak Amplitude 1	R	0h	Amplitude of the First peak discovered by the TDR mechanism on Transmit Channel (TD). The value of these bits is translated into type of cable fault and/or interference.

8.49 CDLAR2 Register (Offset = 186h) [Reset = 0000h]

CDLAR2 Register is shown in Table 8-132.

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Table 8-132 CDLAR2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	RESERVED	R	0h	Reserved

8.50 CDLAR3 Register (Offset = 187h) [Reset = 0000h]

CDLAR3 Register is shown in Table 8-133.

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Table 8-133 CDLAR3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	RESERVED	R	0h	Reserved

8.51 CDLAR4 Register (Offset = 188h) [Reset = 0000h]

CDLAR4 Register is shown in Table 8-134.

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Table 8-134 CDLAR4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	RESERVED	R	0h	Reserved

8.52 CDLAR5 Register (Offset = 189h) [Reset = 0000h]

CDLAR5 Register is shown in Table 8-135.

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Table 8-135 CDLAR5 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	RESERVED	R	0h	Reserved

8.53 CDLAR6 Register (Offset = 18Ah) [Reset = 0000h]

CDLAR6 Register is shown in Table 8-136.

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Table 8-136 CDLAR6 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0h	Reserved
11	TD Peak Polarity 1	R	0h	Polarity of the First peak discovered by the TDR mechanism on Transmit Channel (TD).
10-6	RESERVED	R	0h	Reserved
5	Cross Detect on TD	R	0h	Cross Reflections were detected on TD. Indicate on Short between TD+ and TD-
4	RESERVED	R	0h	Reserved
3	RESERVED	R	0h	Reserved
2	RESERVED	R	0h	Reserved
1-0	RESERVED	R	0h	Reserved

8.54 MSE_Val Register (Offset = 218h) [Reset = 0000h]

MSE_Val is shown in Table 8-137.

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Table 8-137 MSE_Val Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	Mean Square Error	R	0h	Mean square error.

8.55 IO_CFG1 Register (Offset = 302h) [Reset = 0X00h]

IO_CFG1 Register is shown in Table 8-138.

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Table 8-138 IO_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	MaC Impedance Control	R/W	0h	MAC Impedance Control: MAC interface impedance control sets the series termination for the digital pins. 0h = Slow Mode 1h = Fast Mode
13	RESERVED	R/W	0h	Reserved
12-9	RESERVED	R/W	0h	Reserved
8	cfg_crs_dv_vs_rx_dv	RH/W	X	Selects the CRS_DV pin to be operating as CRS_DV or RX_DV in RMII mode. The default determined by strap. 0h = RMII_CRS_DV 1h = RMII_RX_DV
7	RESERVED	R/W	0h	Reserved
6	RESERVED	R	0h	Reserved
5-0	RESERVED	R	0h	Reserved

8.56 LED0 GPIO register Register (Offset = 303h) [Reset = 0008h]

LED0 GPIO register is shown in Table 8-139.

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Table 8-139 LED0 GPIO register Register Field Descriptions

Bit	Field	Type	Reset	Description
15-6	RESERVED	R	0h	Reserved
5-3	cfg_led0_clk_sel	R/W	1h	Selects one of the internal clock, for output on LED0. This is enabled when cfg_led0_gpio_ctrl[2:0] = 001b. The possible configurations are: 0h = Reserved 1h = Reserved 2h = Reserved 3h = Reserved 4h = Reserved 5h = PLL Clock out 6h = Recovered Clock 7h = Reserved
2-0	cfg_led0_gpio_ctrl	R/W	0h	GPIO Configuration for LED0: 0h = LED0 1h = Clock output selected by register field cfg_led0_clk_sel 2h = WoL 3h = 0 4h = Interrupt 5h = 0 6h = 0 7h = 1

8.57 LED1 GPIO register Register (Offset = 304h) [Reset = 000Xh]

LED1 GPIO register is shown in Table 8-140.

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Table 8-140 LED1 GPIO register Register Field Descriptions

Bit	Field	Type	Reset	Description
15-6	RESERVED	R	0h	Reserved
5-3	cfg_led1_clk_sel	R/W	1h	Selects one of the internal clock, for output on LED1. This is enabled when cfg_led1_gpio_ctrl[2:0] = 001b. The possible configurations are: 0h = Reserved 1h = Reserved 2h = Reserved 3h = Reserved 4h = Reserved 5h = PLL Clock out 6h = Recovered Clock 7h = Reserved
2-0	cfg_led1_gpio_ctrl	RH/W	X	GPIO Configuration for LED1. Default determied by STRAP. 0h = LED1 (default in BASIC mode) 1h = Reserved 2h = WoL 3h = Reserved 4h = Interrupt 5h = TX_ER 6h = CLKOUT25M (default in ENHANCED Mode, selectable by Strap) 7h = Reserved

8.58 LED2 register Register (Offset = 305h) [Reset = 0008h]

LED2 register is shown in Table 8-141.

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Table 8-141 LED2 register Register Field Descriptions

Bit	Field	Type	Reset	Description
15-6	RESERVED	R	0h	Reserved
5-3	RESERVED	R/W	0h	Reserved
2-0	RESERVED	RH/W	0h	Reserved

8.59 LED3 register Register (Offset = 306h) [Reset = 0008h]

LED3 register is shown in Table 8-142.

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Table 8-142 LED3 register Register Field Descriptions

Bit	Field	Type	Reset	Description
15-6	RESERVED	R	0h	Reserved
5-3	RESERVED	R/W	0h	Reserved
2-0	RESERVED	R/W	0h	Reserved

8.60 CLK_OUT_LED_STATUS register Register (Offset = 308h) [Reset = 0002h]

CLK_OUT_LED_STATUS register is shown in Table 8-143.

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Table 8-143 CLK_OUT_LED_STATUS register Register Field Descriptions

Bit	Field	Type	Reset	Description
15-1	RESERVED	R/W	0h	Reserved
0	cfg_clkout_25m_off_status	RH	0h	This bit reflects the status of pin 25 0h = CLKOUT is available 1h = LED1 is available

8.61 VOD_CFG1 Register (Offset = 30Bh) [Reset = 3C00h]

VOD_CFG1 Register is shown in Table 8-144.

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Table 8-144 VOD_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	RESERVED	R	0h	Reserved
13-12	cfg_dac_minus_one_val_mdi_5_to_4	R/W	3h	LD data for mlt3 encoded data of minus one in MDI mode. The 6 bit data is split into two fields - {cfg_dac_minus_one_val_mdi_5_to_4, cfg_dac_minus_one_val_mdi_3_to_0} 28h = 150% 29h = 143.75% 2Ah = 137.50% 2Bh = 131.25% 2Ch = 125% 2Dh = 118.75% 2Eh = 112.50% 2Fh = 106.25% 30h = 100% 31h = 93.75% 32h = 87.50% 33h = 81.25% 34h = 75% 35h = 68.75% 36h = 62.50% 37h = 56.25% 38h = 50%
11-6	cfg_dac_minus_one_val_mdix_3_to_0	R/W	30h	LD data for mlt3 encoded data of minus one in MDIX mode. 28h = 150% 29h = 143.75% 2Ah = 137.50% 2Bh = 131.25% 2Ch = 125% 2Dh = 118.75% 2Eh = 112.50% 2Fh = 106.25% 30h = 100% 31h = 93.75% 32h = 87.50% 33h = 81.25% 34h = 75% 35h = 68.75% 36h = 62.50% 37h = 56.25% 38h = 50%
5-0	cfg_dac_zero_val	R/W	0h	LD data for mlt3 encoded data of zero

8.62 VOD_CFG2 Register (Offset = 30Ch) [Reset = 0410h]

VOD_CFG2 Register is shown in Table 8-145.

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Table 8-145 VOD_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	cfg_dac_minus_one_val_mdi_3_to_0	R/W	0h	LD data for mlt3 encoded data of minus one in MDI mode. 6 bit data is split into two fields - {cfg_dac_minus_one_val_mdi_5_to_4, cfg_dac_minus_one_val_mdi_3_to_0} 28h = 150% 29h = 143.75% 2Ah = 137.50% 2Bh = 131.25% 2Ch = 125% 2Dh = 118.75% 2Eh = 112.50% 2Fh = 106.25% 30h = 100% 31h = 93.75% 32h = 87.50% 33h = 81.25% 34h = 75% 35h = 68.75% 36h = 62.50% 37h = 56.25% 38h = 50%
11-6	cfg_dac_plus_one_val_mdi	R/W	10h	LD data for mlt3 encoded data of plus one in MDI mode 08h = 50% 09h = 56.25% 0Ah = 62.50% 0Bh = 68.75% 0Ch = 75% 0Dh = 81.25% 0Eh = 87.50% 0Fh = 93.75% 10h = 100% 11h = 106.25% 12h = 112.50% 13h = 118.75% 14h = 125% 15h = 131.25% 16h = 137.50% 17h = 143.75% 18h = 150%
5-0	cfg_dac_plus_one_val_mdix	R/W	10h	LD data for mlt3 encoded data of plus one in MDIX mode 08h = 50% 09h = 56.25% 0Ah = 62.50% 0Bh = 68.75% 0Ch = 75% 0Dh = 81.25% 0Eh = 87.50% 0Fh = 93.75% 10h = 100% 11h = 106.25% 12h = 112.50% 13h = 118.75% 14h = 125% 15h = 131.25% 16h = 137.50% 17h = 143.75% 18h = 150%

8.63 VOD_CFG3 Register (Offset = 30Eh) [Reset = 8400h]

VOD_CFG3 Register is shown in Table 8-146.

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Table 8-146 VOD_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	ld_term_mdix_10M_reg	R/W	8h	10M mode, MDIX Termination Value Register 0h = 122 1h = 119 2h = 116 3h = 113 4h = 110 5h = 107 6h = 105 7h = 102 8h = 100 9h = 98 Ah = 96 Bh = 94 Ch = 92 Dh = 90 Eh = 88 Fh = 86
11	ld_term_mdix_10M_en	R/W	0h	10M mode, MDIX Termination Value Register Enable 0h = Disable 1h = Enable
10-7	ld_term_mdi_10M_reg	R/W	8h	10M mode, MDI Termination Value Register 0h = 122 1h = 119 2h = 116 3h = 113 4h = 110 5h = 107 6h = 105 7h = 102 8h = 100 9h = 98 Ah = 96 Bh = 94 Ch = 92 Dh = 90 Eh = 88 Fh = 86
6	ld_term_mdi_10M_en	R/W	0h	10M mode, MDI Termination Value Register Enable 0h = Disable 1h = Enable
5-2	RESERVED	R/W	0h	Reserved
1-0	RESERVED	R	0h	Reserved

8.64 ANA_LD_PROG_SL Register (Offset = 404h) [Reset = 0080h]

ANA_LD_PROG_SL Register is shown in Table 8-147.

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Table 8-147 ANA_LD_PROG_SL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	RESERVED	R/W	0h	Reserved

8.65 ANA_RX10BT_CTRL Register (Offset = 40Dh) [Reset = 0008h]

ANA_RX10BT_CTRL Register is shown in Table 8-148.

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Table 8-148 ANA_RX10BT_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-5	RESERVED	R/W	0h	Reserved
4-0	rx10bt_comp_sl	R/W	8h	10B-T current Gain, common for both POS and NEG, Starting from 200mV to 575mV, step size of 25mV

8.66 GENCFG Register (Offset = 456h) [Reset = 0008h]

GENCFG Register is shown in Table 8-149.

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Table 8-149 GENCFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-4	RESERVED	R/W	0h	Reserved
3	Min IPG Enable	R/W	1h	Min IPG Enable: 0h = Minimal IPG set to 200ns 1h = Enable Minimum Interpacket Gap (IPG is set to 120ns instead of 200ns)
2-0	RESERVED	R/W	0h	Reserved

8.67 LEDCFG Register (Offset = 460h) [Reset = 5565h]

LEDCFG Register is shown in Table 8-150.

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Table 8-150 LEDCFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R/W	0h	Reserved
11-8	RESERVED	R/W	0h	Reserved
7-4	RESERVED	R/W	0h	Reserved
3-0	LED1 Control	R/W	5h	LED1 Control:Selects the source for LED1. 0h = LINK OK 1h = RX/TX Activity 2h = TX Activity 3h = RX Activity 4h = Collision 5h = Speed, High for 100BASE-TX 6h = Speed, High for 10BASE-T 7h = Full-Duplex 8h = LINK OK / BLINK on TX/RX Activity 9h = Active Stretch Signal Ah = MII LINK (100BT+FD) Bh = LPI Mode (Energy Efficient Ethernet) Ch = TX/RX MII Error Dh = Link Lost (remains on until register 0x0001 is read) Eh = Blink for PRBS error (remains ON for single error, remains until counter is cleared) Fh = Reserved

8.68 IOCTRL Register (Offset = 461h) [Reset = 0010h]

IOCTRL Register is shown in Table 8-151.

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Table 8-151 IOCTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R/W	0h	Reserved
14	RESERVED	R/W	0h	Reserved
13-12	RESERVED	R/W	0h	Reserved
11	RESERVED	R/W	0h	Reserved
10-7	RESERVED	R/W	0h	Reserved
6-5	RESERVED	R/W	0h	Reserved
4-0	RESERVED	R/W	0h	Reserved

8.69 SOR1 Register (Offset = 467h) [Reset = 0000h]

SOR1 Register is shown in Table 8-152.

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Table 8-152 SOR1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	RESERVED	R	0h	Reserved
11	RX_CLK Strapping Value	RH	0h	Strap on RX_CLK 0h = active low, 1h = active high
10	RESERVED	RH	0h	Reserved
9	RESERVED	RH	0h	Reserved
8	RMII_EN Strapping Value	RH	0h	Strap on RMII_EN 0h = active low, 1h = active high
7	RX_D3 Strapping Value	RH	0h	Strap on RX_D3 0h = active low, 1h = active high
6	RX_ER/LED1_EN Strapping Value	RH	0h	Strap on RX_ER/LED1_EN 0h = active low, 1h = active high
5	RF_EN Strapping Value	RH	0h	Strap on RF_EN 0h = active low, 1h = active high
4	RESERVED	RH	0h	Reserved
3	RESERVED	RH	0h	Reserved
2	LED0 Strapping Value	RH	0h	Strap on LED0 0h = active low, 1h = active high
1	LED1/CLKOUT Strapping Value	RH	0h	Strap on LED1/CLKOUT 0h = active low, 1h = active high
0	RESERVED	RH	0h	Reserved

8.70 SOR2 Register (Offset = 468h) [Reset = 0287h]

SOR2 Register is shown in Table 8-153.

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Table 8-153 SOR2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved
14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	CRS_DV_vs_RX_DV	RH	0h	RMII mode RX_DV pin as CRS_DV or RX_DV 0h = RMI CRS_DV 1h = RMII RX_DV
11	RESERVED	R	0h	Reserved
10	RESERVED	R	0h	Reserved
9	CFG_LED_LINK_POL	RH	1h	Link LED Polarity Detection, reflects the LED0 Polarity 0h = Active Low polarity setting 1h = Active High polarity setting
8	CFG_FLD_EN	RH	0h	Status of Fast Link Drop. 0h = FLD Disabled 1h = FLD Enabled. See CR3[10,3:0] for more information
7	CFG_AMDIX	RH	1h	AMDIX Enable. 0h = AMDIX Disable 1h = AMDIX Enable
6	RESERVED	R	0h	Reserved
5	LED_SPEED_POL	RH	0h	Speed LED Polarity Detection, reflects the LED1 Polarity 0h = Active Low polarity setting 1h = Active High polarity setting
4	CFG_RMII_MODE	RH	0h	MII/RMII mode Selection 0h = MII 1h = RMII
3	CFG_XI_50_Follower	RH	0h	RMII Leader / Follower mode Selection 0h = RMII Leader Mode 1h = RMII Follower Mode
2	CFG_AN_1	R	1h	This is to derive ANAR register bit [8:5]
1	CFG_AN_0	R	1h	This is to derive ANAR register bit [8:5]
0	CFG_AN_EN	R	1h	ANEG Enable.

8.71 LEDCFG2 Register (Offset = 469h) [Reset = 0XXXh]

LEDCFG2 Register is shown in Table 8-154.

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Table 8-154 LEDCFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-11	RESERVED	R	0h	Reserved
10	RESERVED	R	X	Reserved
9	RESERVED	R	0h	Reserved
8	RESERVED	R	0h	Reserved
7	RESERVED	R	0h	Reserved
6	RESERVED	R	X	Reserved
5	RESERVED	R	0h	Reserved
4	RESERVED	R	0h	Reserved
3	RESERVED	R	0h	Reserved
2	LED1_polarity	RH/W	X	led 1 polarity. Default determined by strap. 0h = active low, 1h = active high
1	LED1_drv_val	R/W	0h	led1 drive value
0	LED1_drv_en	R/W	0h	led 1 drive enable 0h = Normal operation 1h = drive LED polarity,

8.72 RXFCFG1 Register (Offset = 4A0h) [Reset = 10X1h]

RXFCFG1 Register is shown in Table 8-155.

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Table 8-155 RXFCFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	RESERVED	R	0h	Reserved
13	RESERVED	R	0h	Reserved
12	CRC Gate	R/W	1h	CRC Gate: If Magic Packet has Bad CRC then no indication (status, interrupt, GPIO) when enabled. 0h = Bad CRC does not gate Magic Packet or Pattern Indications 1h = Bad CRC gates Magic Packet and Pattern Indications
11	WoL Level Change Indication Clear	W0C	0h	WoL Level Change Indication Clear: If WoL Indication is set for Level change mode, this bit clears the level upon a write. 0h = Clear
10-9	WoL Pulse Indication Select	R/W	0h	WoL Pulse Indication Select: Only valid when WoL Indication is set for Pulse mode. 0h = 8 clock cycles (of 125MHz clock) 1h = 16 clock cycles 2h = 32 clock cycles 3h = 64 clock cycles
8	WoL Indication Select	R/W	0h	WoL Indication Select: 0h = Pulse mode 1h = Level change mode
7	WoL Enable	RH/W	X	WoL Enable. Default from strap in BASIC mode. Defaults to 1 in Enhanced mode. 0h = normal operation 1h = Enable Wake-on-LAN (WoL)
6	Bit Mask Flag	R/W	0h	Bit Mask Flag
5	Secure-ON Enable	R/W	0h	Enable Secure-ON password for Magic Packets
4	RESERVED	R	0h	Reserved
3	RESERVED	R	0h	Reserved
2	RESERVED	R	0h	Reserved
1	RESERVED	R	0h	Reserved
0	WoL Magic Packet Enable	RH/W	1h	Enable Interrupt upon reception of Magic Packet. Default from strap

8.73 RXFS Register (Offset = 4A1h) [Reset = 1000h]

RXFS Register is shown in Table 8-156.

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Table 8-156 RXFS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	RESERVED	R	0h	Reserved
12	WoL Interrupt Source	R/W	1h	WoL Interrupt Source: Source of Interrupt for bit [1] of register 0x0013. When enabling WoL, this bit is automatically set to WoL Interrupt. 0h = Data Polarity Interrupt 1h = WoL Interrupt
11-8	RESERVED	R	0h	Reserved
7	SFD Error	RCH	0h	SFD Error. Latched high and cleared on read. 0h = No SFD error 1h = Packet with SFD error (without the SFD byte indicated in bit [13] register 0x04A0)
6	Bad CRC	RCH	0h	Bad CRC. Latched high and cleared on read. 0h = No bad CRC received 1h = Bad CRC was received
5	Secure-On Hack Flag	RCH	0h	Secure-ON Hack Flag. Latched high and cleared on read. 0h = Valid Secure-ON Password 1h = Invalid Password detected in Magic Packet
4	RESERVED	RCH	0h	Reserved
3	RESERVED	RCH	0h	Reserved
2	RESERVED	RCH	0h	Reserved
1	RESERVED	RCH	0h	Reserved
0	WoL Magic Packet Status	RCH	0h	WoL Magic Packet Status. Latched high and cleared on read.

8.74 RXFPMD1 Register (Offset = 4A2h) [Reset = 0000h]

RXFPMD1 Register is shown in Table 8-157.

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Table 8-157 RXFPMD1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	MAC Destination Address Byte 4	R/W	0h	Perfect Match Data: Configured for MAC Destination Address
7-0	MAC Destination Address Byte 5 (MSB)	R/W	0h	Perfect Match Data: Configured for MAC Destination Address

8.75 RXFPMD2 Register (Offset = 4A3h) [Reset = 0000h]

RXFPMD2 Register is shown in Table 8-158.

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Table 8-158 RXFPMD2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	MAC Destination Address Byte 2	R/W	0h	Perfect Match Data: Configured for MAC Destination Address
7-0	MAC Destination Address Byte 3	R/W	0h	Perfect Match Data: Configured for MAC Destination Address

8.76 RXFPMD3 Register (Offset = 4A4h) [Reset = 0000h]

RXFPMD3 Register is shown in Table 8-159.

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Table 8-159 RXFPMD3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	MAC Destination Address Byte 0	R/W	0h	Perfect Match Data: Configured for MAC Destination Address
7-0	MAC Destination Address Byte 1	R/W	0h	Perfect Match Data: Configured for MAC Destination Address

8.77 RXFSOP1 Register (Offset = 4A5h) [Reset = 0000h]

RXFSOP1 Register is shown in Table 8-160.

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Table 8-160 RXFSOP1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	Secure-ON Password Byte 1	R/W	0h	Secure-ON Password Select: Secure-ON password for Magic Packets
7-0	Secure-ON Password Byte 0	R/W	0h	Secure-ON Password Select: Secure-ON password for Magic Packets

8.78 RXFSOP2 Register (Offset = 4A6h) [Reset = 0000h]

RXFSOP2 Register is shown in Table 8-161.

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Table 8-161 RXFSOP2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	Secure-ON Password Byte 3	R/W	0h	Secure-ON Password Select: Secure-ON password for Magic Packets
7-0	Secure-ON Password Byte 2	R/W	0h	Secure-ON Password Select: Secure-ON password for Magic Packets

8.79 RXFSOP3 Register (Offset = 4A7h) [Reset = 0000h]

RXFSOP3 Register is shown in Table 8-162.

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Table 8-162 RXFSOP3 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	Secure-ON Password Byte 5	R/W	0h	Secure-ON Password Select: Secure-ON password for Magic Packets
7-0	Secure-ON Password Byte 4	R/W	0h	Secure-ON Password Select: Secure-ON password for Magic Packets