SNLS603D December   2020  – April 2025 DP83TG720R-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1.     Pin Functions
    2. 5.1 Pin States
    3. 5.2 Pin Power Domain
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 LED Drive Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Diagnostic Tool Kit
        1. 7.3.1.1 Signal Quality Indicator
        2. 7.3.1.2 Time Domain Reflectometry
        3. 7.3.1.3 Built-In Self-Test For Datapath
          1. 7.3.1.3.1 Loopback Modes
          2. 7.3.1.3.2 Data Generator
          3. 7.3.1.3.3 Programming Datapath BIST
        4. 7.3.1.4 Temperature and Voltage Sensing
        5. 7.3.1.5 Electrostatic Discharge Sensing
      2. 7.3.2 Compliance Test Modes
        1. 7.3.2.1 Test Mode 1
        2. 7.3.2.2 Test Mode 2
        3. 7.3.2.3 Test Mode 4
        4. 7.3.2.4 Test Mode 5
        5. 7.3.2.5 Test Mode 6
        6. 7.3.2.6 Test Mode 7
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down
      2. 7.4.2 Reset
      3. 7.4.3 Standby
      4. 7.4.4 Normal
      5. 7.4.5 Sleep
      6. 7.4.6 State Transitions
        1. 7.4.6.1 State Transition #1 - Standby to Normal
        2. 7.4.6.2 State Transition #2 - Normal to Standby
        3. 7.4.6.3 State Transition #3 - Normal to Sleep
        4. 7.4.6.4 State Transition #4 - Sleep to Normal
      7. 7.4.7 Media Dependent Interface
        1. 7.4.7.1 MDI Master and MDI Slave Configuration
        2. 7.4.7.2 Auto-Polarity Detection and Correction
      8. 7.4.8 MAC Interfaces
        1. 7.4.8.1 Reduced Gigabit Media Independent Interface
      9. 7.4.9 Serial Management Interface
        1. 7.4.9.1 Direct Register Access
        2. 7.4.9.2 Extended Register Space Access
          1. 7.4.9.2.1 Write Operation (No Post Increment)
          2. 7.4.9.2.2 Read Operation (No Post Increment)
          3. 7.4.9.2.3 Write Operation (Post Increment)
          4. 7.4.9.2.4 Read Operation (Post Increment)
    5. 7.5 Programming
      1. 7.5.1 Strap Configuration
      2. 7.5.2 LED Configuration
      3. 7.5.3 PHY Address Configuration
    6. 7.6 Register Maps
      1. 7.6.1 Register Access Summary
      2. 7.6.2 DP83TG720 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
    3. 8.3 Power Supply Recommendations
    4. 8.4 Compatibility with TI's 100BT1 PHY
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Signal Traces
        2. 8.5.1.2 Return Path
        3. 8.5.1.3 Physical Medium Attachment
        4. 8.5.1.4 Metal Pour
        5. 8.5.1.5 PCB Layer Stacking
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Option Addendum
      1. 11.1.1 Packaging Information
      2. 11.1.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.8.1 Reduced Gigabit Media Independent Interface

The DP83TG720R-Q1 also supports Reduced Gigabit Media Independent Interface (RGMII) as specified by RGMII version 2.0. RGMII is designed to reduce the number of pins required to connect MAC and PHY. To accomplish this goal, the control signals are multiplexed. Both rising and falling edges of the clock are used to sample the control signal pin on transmit and receive paths. For 1Gbps operation, RX_CLK and TX_CLK operate at 125MHz.

The RGMII signals are summarized in Table 7-9:

Table 7-9 RGMII Signals
FUNCTIONPINS
Data SignalsTX_D[3:0]
RX_D[3:0]
Control SignalsTX_CTRL
RX_CTRL
Clock SignalsTX_CLK
RX_CLK
DP83TG720R-Q1 RGMII ConnectionsFigure 7-13 RGMII Connections
Table 7-10 RGMII Transmit Encoding
TX_CTRL
(POSITIVE EDGE)		TX_CTRL
(NEGATIVE EDGE)		TX_D[3:0]DESCRIPTION
000000 through 1111Normal Inter-Frame
010000 through 1111Reserved
100000 through 1111Normal Data Transmission
110000 through 1111Transmit Error Propagation
Table 7-11 RGMII Receive Encoding
RX_CTRL
(POSITIVE EDGE)		RX_CTRL
(NEGATIVE EDGE)		RX_D[3:0]DESCRIPTION
000000 through 1111Normal Inter-Frame
010000 through 1101Reserved
011110False Carrier Indication
011111Reserved
100000 through 1111Normal Data Reception
110000 through 1111Data Reception with Errors

The DP83TG720R-Q1 supports in-band status indication to help simplify link status detection. Inter-frame signals on RX_D[3:0] pins as specified in Table 7-12.

Table 7-12 RGMII In-Band Status
RX_CTRLRX_D3RX_D[2:1]RX_D0
0

Note:

In-band status is only valid when RX_CTRL is low		Duplex Status:

0 = Half-Duplex

1 = Full-Duplex

RX_CLK Clock Speed:

00 = 2.5MHz

01 = 25MHz

10 = 125MHz

11 = Reserved

Link Status:

0 = Link not established

1 = Valid link established

RGMII MAC Interface for Gigabit Ethernet has stringent timing requirements to meet system level performance. To meet these timing requirements and to operate with different MACs over RGMII, the following requirements must be taken into consideration when designing PCB. TI recommends to check board level signal integrity by using the DP83TG720 IBIS model.

RGMII-TX Requirements

  • RGMII TX signals routed with controlled impedance of 50Ohm +/-15%.
  • Max routing length limited to 5inches for better signal integrity performance.
  • Figure 7-14 shows a RGMII interface requirements for TX* signals. MAC RGMII driver output impedance of 50Ohm+/-20%.
  • Skew for all RGMII TX signals at TP2, in Figure 7-14, less than ±500ps.
  • Signal Integrity at TP1 and TP2, in Figure 7-14, can be verified with IBIS model simulation, that the following requirements are met:
    • At TP2, signal meeting rise/fall time of 1ns (20-80%) of signal amplitude.
    • Rise/fall time is monotonic between VIH/VIL level at TP2.
DP83TG720R-Q1 RGMII TX RequirementsFigure 7-14 RGMII TX Requirements

RGMII-RX Requirements

  • RGMII RX signals routed with controlled impedance of 50Ohm +/-15%.
  • Max routing length limited to 5inch for better signal integrity performance.
  • No damping resistors added at TP3/TP4, in Figure 7-15, as that can impact signal integrity of RX signals.
  • Figure 7-15 shows a RGMII interface requirements for RX* signals. MAC RGMII driver output impedance is 50Ohm+/-20%.
  • Signal Integrity at TP3 and TP4, in Figure 7-15, can be verified with IBIS model simulation, that the following requirements are met:
    • At TP4, signal meeting rise/fall time of 1ns (20-80%) of signal amplitude.
    • Rise/fall time is monotonic between VIH/VIL level at TP4.
DP83TG720R-Q1 RGMII RX RequirementsFigure 7-15 RGMII RX Requirements
Note:
  1. We recommend routing RGMII on buried traces to minimize EMC emissions.
  2. Buried traces connected with via placement as close as possible to the PHY and MAC.