SNLS603D December   2020  – April 2025 DP83TG720R-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1.     Pin Functions
    2. 5.1 Pin States
    3. 5.2 Pin Power Domain
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 LED Drive Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Diagnostic Tool Kit
        1. 7.3.1.1 Signal Quality Indicator
        2. 7.3.1.2 Time Domain Reflectometry
        3. 7.3.1.3 Built-In Self-Test For Datapath
          1. 7.3.1.3.1 Loopback Modes
          2. 7.3.1.3.2 Data Generator
          3. 7.3.1.3.3 Programming Datapath BIST
        4. 7.3.1.4 Temperature and Voltage Sensing
        5. 7.3.1.5 Electrostatic Discharge Sensing
      2. 7.3.2 Compliance Test Modes
        1. 7.3.2.1 Test Mode 1
        2. 7.3.2.2 Test Mode 2
        3. 7.3.2.3 Test Mode 4
        4. 7.3.2.4 Test Mode 5
        5. 7.3.2.5 Test Mode 6
        6. 7.3.2.6 Test Mode 7
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down
      2. 7.4.2 Reset
      3. 7.4.3 Standby
      4. 7.4.4 Normal
      5. 7.4.5 Sleep
      6. 7.4.6 State Transitions
        1. 7.4.6.1 State Transition #1 - Standby to Normal
        2. 7.4.6.2 State Transition #2 - Normal to Standby
        3. 7.4.6.3 State Transition #3 - Normal to Sleep
        4. 7.4.6.4 State Transition #4 - Sleep to Normal
      7. 7.4.7 Media Dependent Interface
        1. 7.4.7.1 MDI Master and MDI Slave Configuration
        2. 7.4.7.2 Auto-Polarity Detection and Correction
      8. 7.4.8 MAC Interfaces
        1. 7.4.8.1 Reduced Gigabit Media Independent Interface
      9. 7.4.9 Serial Management Interface
        1. 7.4.9.1 Direct Register Access
        2. 7.4.9.2 Extended Register Space Access
          1. 7.4.9.2.1 Write Operation (No Post Increment)
          2. 7.4.9.2.2 Read Operation (No Post Increment)
          3. 7.4.9.2.3 Write Operation (Post Increment)
          4. 7.4.9.2.4 Read Operation (Post Increment)
    5. 7.5 Programming
      1. 7.5.1 Strap Configuration
      2. 7.5.2 LED Configuration
      3. 7.5.3 PHY Address Configuration
    6. 7.6 Register Maps
      1. 7.6.1 Register Access Summary
      2. 7.6.2 DP83TG720 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
    3. 8.3 Power Supply Recommendations
    4. 8.4 Compatibility with TI's 100BT1 PHY
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Signal Traces
        2. 8.5.1.2 Return Path
        3. 8.5.1.3 Physical Medium Attachment
        4. 8.5.1.4 Metal Pour
        5. 8.5.1.5 PCB Layer Stacking
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Option Addendum
      1. 11.1.1 Packaging Information
      2. 11.1.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Timing Requirements

(1)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
POWER-UP TIMING
T5.1 VDDA3P3 Duration(2) 0% to 100% (+/- 10% VDDA3P3) 0.5 40 ms
T5.2 VDD1P0 Duration(2) 0% to 100% (+/- 10% VDD1P0) 0.1 40 ms
T5.2 VDDIO Duration(2) VDDIO = 1.8V 0.1 40 ms
T5.2 VDDIO Duration(2) VDDIO = 2.5V 0.1 40 ms
T5.2 VDDIO Duration(2) VDDIO = 3.3V 0.1 40 ms
T5.2 VSLEEP Duration(2) 0% to 100% (+/- 10% VSLEEP) 0.1 40 ms
T5.3 Crystal stabilization-time post power-up (from last power rail ramp to 100%) 1500 µs
T5.4 Osillator stabilization-time post power-up ( from last power rail ramp  to 100%)(3) 20 ms
T5.5 Post power-up stabilization-time prior to MDC preamble for register access 65 ms
T5.6 Hardware configuration latch-in time from power-up 60 ms
T5.7 Hardware configuration pins transition to functional mode from latch-in completion 110 ns
T5.8 PAM3 IDLE Stream from power-up (Master Mode) 60 ms
RESET TIMING (RESET_N)
T6.1 RESET pulse width 5 µs
T6.2 Post reset stabilization-time prior to MDC preamble for register access 1 ms
T6.3 Hardware configuration latch-in time from reset 2 µs
T6.4 Hardware configuration pins transition to functional mode from latch-in completion 1.5 µs
T6.5 PAM3 IDLE Stream from reset (Master Mode) 1500 µs
SMI TIMING
T4.1 MDC to MDIO (Output) Delay Time (25 pF load) 0 6 10 ns
T4.2 MDIO (Input) to MDC Setup Time 10 ns
T4.3 MDIO (Input) to MDC Hold Time 10 ns
MDC Frequency ( 25 pF load) 2.5 20 MHz
RECEIVE LATENCY TIMING
SSD symbol on MDI to Rising edge of RGMII RX_CLK with assertion of RX_CTRL 8 µs
SSD symbol on MDI to Rising edge of RGMII RX_CLK with assertion of RX_CTRL (RS-FEC bypass mode) 400 ns
TRANSMIT LATENCY TIMING
RGMII Rising edge TX_CLK with assertion TX_CTRL to SSD symbol on MDI 0.8 µs
RGMII Rising edge TX_CLK with assertion TX_CTRL to SSD symbol on MDI (RS-FEC bypass mode) 600 ns
25MHz OSCILLATOR REQUIREMENTS
Frequency (XI) 25 MHz
Frequency Tolerance and Stability Over temperature and aging –100 100 ppm
Rise / Fall Time (10% - 90%)(6) 8 ns
Jitter (RMS) Integrated upto 5MHz 1 ps
Duty Cycle 40 50 60 %
RGMII TIMING
TsetupR TX_D[3:0], TX_CTRL Setup to TX_CLK on PHY pins 1 2 ns
TholdR TX_D[3:0], TX_CTRL Hold from TX_CLK (5) on PHY pins 1 2 ns
TskewT RX_D[3:0], RX_CTRL Delay from RX_CLK (Align Mode Enabled) On PHY Pins -500 0 500 ps
TskewT (Shift) RX_D[3:0], RX_CTRL Delay from RX_CLK (Shift Mode Enabled, default)(4) On PHY Pins 2.190 2.650 2.970 ns
Tcyc Clock Cycle Duration RX_CLK 7.2 8 8.8 ns
Tcyc Clock Cycle Duration TX_CLK 7.2 8 8.8 ns
Duty_G Duty Cycle RX_CLK 45 50 55 %
Duty_G Duty Cycle TX_CLK 45 50 55 %
Tr Rise Time  (20% - 80%) CL=Ctrace=5pF 0.75 ns
Tf Fall Time (20% - 80%) CL=Ctrace = 5pF 0.75 ns
RGMII RX Shift Mode Delays DLL DLL_RX_DELAY_CTRL_SL=0(4) 0.330 0.650 0.970 ns
DLL DLL_RX_DELAY_CTRL_SL=1(4) 0.580 0.900 1.220 ns
 DLL DLL_RX_DELAY_CTRL_SL=2(4) 0.830 1.150 1470 ns
DLL DLL_RX_DELAY_CTRL_SL=3(4) 1.000 1.400 1.720 ns
DLL DLL_RX_DELAY_CTRL_SL=4(4) 1.230 1.650 1.970 ns
DLL DLL_RX_DELAY_CTRL_SL=5(4) 1.490 1.990 2.220 ns
DLL DLL_RX_DELAY_CTRL_SL=6(4) 1.690 2.150 2.470 ns
 DLL DLL_RX_DELAY_CTRL_SL=7(4) 1.960 2.400 2.730 ns
 DLL DLL_RX_DELAY_CTRL_SL=8(4) 2.180 2.650 2.970 ns
 DLL DLL_RX_DELAY_CTRL_SL=9(4) 2.490 2.900 3.220 ns
RGMII Shift TX Mode Delays
DLL DLL_TX_DELAY_CTRL_SL=1(4) (7) 0.08 0.25 0.38 ns
DLL DLL_TX_DELAY_CTRL_SL=2(4) (7) 0.27 0.49 0.67 ns
DLL DLL_TX_DELAY_CTRL_SL=3(4) (7) 0.51 0.73 0.91 ns
DLL DLL_TX_DELAY_CTRL_SL=4(4) (7) 0.75 0.97 1.15 ns
DLL DLL_TX_DELAY_CTRL_SL=5(4) (7) 0.94 1.21 1.44 ns
DLL DLL_TX_DELAY_CTRL_SL=6(4) (7) 1.18 1.45 1.68 ns
 DLL DLL_TX_DELAY_CTRL_SL=7(4) (7) 1.37 1.69 1.98 ns
DLL DLL_TX_DELAY_CTRL_SL=8(4) (7) 1.61 1.93 2.22 ns
DLL DLL_TX_DELAY_CTRL_SL=9(4) (7) 1.85 2.17 2.46 ns
DLL DLL_TX_DELAY_CTRL_SL=10(4) (7) 2.04 2.42 2.75 ns
DLL DLL_TX_DELAY_CTRL_SL=11(4) (7) 2.28 2.65 2.99 ns
DLL DLL_TX_DELAY_CTRL_SL=12(4) (7) 2.52 2.9 3.23 ns
25MHz CRYSTAL REQUIREMENTS
Frequency 25 MHz
Frequency Tolerance and Stability Over temperature and aging –100 100 ppm
Equivalent Series Resistance 100 Ω
OUTPUT CLOCK TIMING (CLKOUT)
Frequency 25 MHz
Duty Cycle ( With crystal attached) 45 55 %
Rise / Fall Time (10% - 90%) 2.5 ns
Jitter (RMS) (Slave Mode, MAC Iinterface : SGMII) 5 ps
Jitter (RMS) (Master Mode, MAC Iinterface : SGMII) 2.4 ps
Jitter (RMS) (Slave Mode, MAC Interface : RGMII) 11 ps
Jitter (RMS) (Master Mode, MAC Interface : RGMII) 15 ps
Sleep Entry and Wake-Up
WAKE LOW to Sleep Entry; INH Transition LOW Normal Mode, MDI_Energy = FALSE sleep_en = TRUE 64 85 us
sleep_en = True to Sleep Entry; INH Transition LOW (master mode) Normal Mode, WAKE = LOW, MDI_Energy = FALSE 5 85 us
sleep_en = True to Sleep Entry; INH Transition LOW (slave mode) Normal Mode, WAKE = LOW, MDI_Energy = FALSE 5000 us
MDI Energy Loss to Sleep Entry; INH Transition LOW Normal Mode, WAKE = LOW, sleep_en = TRUE 5 ms
Local Wake-Up Pulse Duration (on Wake pin) Sleep Mode, WAKE pin 80 µs
Send-S/Send-T pattern duration for wake up from MDI Sleep Mode, Slave 1.25 ms
Local Wake-Up; INH Transition HIGH Sleep Mode, rising edge of WAKE pin to rising edge of INH 85 us
Tolerable differential noise level on MDI for PHY to stay in sleep mode Sleep Mode 200 mV pk-pk
Link-partner's VOD for valid wake-up (for 5m cable) Sleep Mode 840 mV pk-pk
(1) Verified by production test or characterization or design.
(2) No supply sequencing constraint across power rails
(3) In case OSC clock is delayed, additional reset is needed post Osc clock stablisation
(4) Refer register[0x0430] for programmability of RX and TX delay codes
(5) PHY provides internal delays on TX_CLK to TX_D[3:0] to add additional skew upto 2ns. Refer to register[0x0430] for programmability
(6) Max rise/fall time of 8ns is supported for duty cycle of 40% to 55%. Max rise/fall time of 6ns is supported for duty cycle of 40% to 60% 
(7) Data for 1.8V VDDIO.