SPRS975H August   2016  – February 2020 DRA780 , DRA781 , DRA782 , DRA783 , DRA784 , DRA785 , DRA786 , DRA787 , DRA788

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  SD_DAC
      4. 4.3.4  ADC
      5. 4.3.5  Camera Control
      6. 4.3.6  CPI
      7. 4.3.7  CSI2
      8. 4.3.8  EMIF
      9. 4.3.9  GPMC
      10. 4.3.10 Timers
      11. 4.3.11 I2C
      12. 4.3.12 UART
      13. 4.3.13 McSPI
      14. 4.3.14 QSPI
      15. 4.3.15 McASP
      16. 4.3.16 DCAN and MCAN
      17. 4.3.17 GMAC_SW
      18. 4.3.18 SDIO Controller
      19. 4.3.19 GPIO
      20. 4.3.20 PWMSS
      21. 4.3.21 ATL
      22. 4.3.22 Test Interfaces
      23. 4.3.23 System and Miscellaneous
        1. 4.3.23.1 Sysboot
        2. 4.3.23.2 Power, Reset and Clock Management (PRCM)
        3. 4.3.23.3 Enhanced Direct Memory Access (EDMA)
        4. 4.3.23.4 Interrupt Controllers (INTC)
      24. 4.3.24 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power-On Hours (POH)
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Operating Performance Points
      1. 5.5.1 AVS Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6 Power Consumption Summary
    7. 5.7 Electrical Characteristics
      1. Table 5-6  LVCMOS DDR DC Electrical Characteristics
      2. Table 5-7  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-8  IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-9  IHHV1833 Buffers DC Electrical Characteristics
      5. Table 5-10 LVCMOS Analog OSC Buffers DC Electrical Characteristics
      6. Table 5-11 Dual Voltage LVCMOS DC Electrical Characteristics
      7. Table 5-12 Analog-to-Digital ADC Subsystem Electrical Specifications
    8. 5.8 Thermal Characteristics
      1. 5.8.1 Package Thermal Characteristics
    9. 5.9 Timing Requirements and Switching Characteristics
      1. 5.9.1 Timing Parameters and Information
        1. 5.9.1.1 Parameter Information
          1. 5.9.1.1.1 1.8 V and 3.3 V Signal Transition Levels
          2. 5.9.1.1.2 1.8 V and 3.3 V Signal Transition Rates
          3. 5.9.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.9.2 Interface Clock Specifications
        1. 5.9.2.1 Interface Clock Terminology
        2. 5.9.2.2 Interface Clock Frequency
      3. 5.9.3 Power Supply Sequences
      4. 5.9.4 Clock Specifications
        1. 5.9.4.1 Input Clocks / Oscillators
          1. 5.9.4.1.1 OSC0 External Crystal
          2. 5.9.4.1.2 OSC0 Input Clock
          3. 5.9.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.9.4.1.3.1 OSC1 External Crystal
            2. 5.9.4.1.3.2 OSC1 Input Clock
          4. 5.9.4.1.4 RC On-die Oscillator Clock
        2. 5.9.4.2 Output Clocks
        3. 5.9.4.3 DPLLs, DLLs
          1. 5.9.4.3.1 DPLL Characteristics
          2. 5.9.4.3.2 DLL Characteristics
            1. 5.9.4.3.2.1 DPLL and DLL Noise Isolation
      5. 5.9.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.9.6 Peripherals
        1. 5.9.6.1  Timing Test Conditions
        2. 5.9.6.2  VIP
        3. 5.9.6.3  DSS
        4. 5.9.6.4  EMIF
        5. 5.9.6.5  GPMC
          1. 5.9.6.5.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.9.6.5.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.9.6.5.3 GPMC/NAND Flash Interface Asynchronous Timing
        6. 5.9.6.6  GP Timers
          1. 5.9.6.6.1 GP Timer Features
        7. 5.9.6.7  I2C
          1. Table 5-39 Timing Requirements for I2C Input Timings
          2. Table 5-40 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        8. 5.9.6.8  UART
          1. Table 5-41 Timing Requirements for UART
          2. Table 5-42 Switching Characteristics Over Recommended Operating Conditions for UART
        9. 5.9.6.9  McSPI
        10. 5.9.6.10 QSPI
        11. 5.9.6.11 McASP
          1. Table 5-50 Timing Requirements for McASP1
          2. Table 5-51 Timing Requirements for McASP2
          3. Table 5-52 Timing Requirements for McASP3
          4. Table 5-53 Switching Characteristics Over Recommended Operating Conditions for McASP1
          5. Table 5-54 Switching Characteristics Over Recommended Operating Conditions for McASP2
          6. Table 5-55 Switching Characteristics Over Recommended Operating Conditions for McASP3
        12. 5.9.6.12 DCAN and MCAN
          1. 5.9.6.12.1 DCAN
          2. 5.9.6.12.2 MCAN
          3. Table 5-58 Timing Requirements for CAN Receive
          4. Table 5-59 Switching Characteristics Over Recommended Operating Conditions for CAN Transmit
        13. 5.9.6.13 GMAC_SW
          1. 5.9.6.13.1 GMAC MDIO Interface Timings
          2. 5.9.6.13.2 GMAC RGMII Timings
            1. Table 5-63 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-64 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-65 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-66 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        14. 5.9.6.14 SDIO Controller
          1. 5.9.6.14.1 MMC, SD Default Speed
          2. 5.9.6.14.2 MMC, SD High Speed
          3. 5.9.6.14.3 MMC, SD and SDIO SDR12 Mode
          4. 5.9.6.14.4 MMC, SD SDR25 Mode
        15. 5.9.6.15 GPIO
        16. 5.9.6.16 ATL
          1. 5.9.6.16.1 ATL Electrical Data/Timing
            1. Table 5-77 Switching Characteristics Over Recommended Operating Conditions for ATL_CLKOUTx
      7. 5.9.7 Emulation and Debug Subsystem
        1. 5.9.7.1 JTAG Electrical Data/Timing
          1. Table 5-78 Timing Requirements for IEEE 1149.1 JTAG
          2. Table 5-79 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
          3. Table 5-80 Timing Requirements for IEEE 1149.1 JTAG With RTCK
          4. Table 5-81 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.9.7.2 Trace Port Interface Unit (TPIU)
          1. 5.9.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Processor Subsystems
      1. 6.2.1 DSP Subsystem
      2. 6.2.2 IPU
    3. 6.3 Accelerators and Coprocessors
      1. 6.3.1 EVE
    4. 6.4 Other Subsystems
      1. 6.4.1 Memory Subsystem
        1. 6.4.1.1 EMIF
        2. 6.4.1.2 GPMC
        3. 6.4.1.3 ELM
        4. 6.4.1.4 OCMC
      2. 6.4.2 Interprocessor Communication
        1. 6.4.2.1 Mailbox
        2. 6.4.2.2 Spinlock
      3. 6.4.3 Interrupt Controller
      4. 6.4.4 EDMA
      5. 6.4.5 Peripherals
        1. 6.4.5.1  VIP
        2. 6.4.5.2  DSS
        3. 6.4.5.3  ATL
        4. 6.4.5.4  ADC
        5. 6.4.5.5  Timers
          1. 6.4.5.5.1 General-Purpose Timers
          2. 6.4.5.5.2 32-kHz Synchronized Timer (COUNTER_32K)
        6. 6.4.5.6  I2C
        7. 6.4.5.7  UART
        8. 6.4.5.8  McSPI
        9. 6.4.5.9  QSPI
        10. 6.4.5.10 McASP
        11. 6.4.5.11 DCAN
        12. 6.4.5.12 MCAN
        13. 6.4.5.13 GMAC_SW
        14. 6.4.5.14 SDIO
        15. 6.4.5.15 GPIO
        16. 6.4.5.16 ePWM
        17. 6.4.5.17 eCAP
        18. 6.4.5.18 eQEP
      6. 6.4.6 On-Chip Debug
  7. 7Applications, Implementation, and Layout
    1. 7.1 Introduction
      1. 7.1.1 Initial Requirements and Guidelines
    2. 7.2 Power Optimizations
      1. 7.2.1 Step 1: PCB Stack-up
      2. 7.2.2 Step 2: Physical Placement
      3. 7.2.3 Step 3: Static Analysis
        1. 7.2.3.1 PDN Resistance and IR Drop
      4. 7.2.4 Step 4: Frequency Analysis
      5. 7.2.5 System ESD Generic Guidelines
        1. 7.2.5.1 System ESD Generic PCB Guideline
        2. 7.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
        3. 7.2.5.3 ESD Protection System Design Consideration
      6. 7.2.6 EMI / EMC Issues Prevention
        1. 7.2.6.1 Signal Bandwidth
        2. 7.2.6.2 Signal Routing
          1. 7.2.6.2.1 Signal Routing-Sensitive Signals and Shielding
          2. 7.2.6.2.2 Signal Routing-Outer Layer Routing
        3. 7.2.6.3 Ground Guidelines
          1. 7.2.6.3.1 PCB Outer Layers
          2. 7.2.6.3.2 Metallic Frames
          3. 7.2.6.3.3 Connectors
          4. 7.2.6.3.4 Guard Ring on PCB Edges
          5. 7.2.6.3.5 Analog and Digital Ground
    3. 7.3 Core Power Domains
      1. 7.3.1 General Constraints and Theory
      2. 7.3.2 Voltage Decoupling
      3. 7.3.3 Static PDN Analysis
      4. 7.3.4 Dynamic PDN Analysis
      5. 7.3.5 Power Supply Mapping
      6. 7.3.6 DPLL Voltage Requirement
      7. 7.3.7 Loss of Input Power Event
      8. 7.3.8 Example PCB Design
        1. 7.3.8.1 Example Stack-up
        2. 7.3.8.2 vdd_dspeve Example Analysis
    4. 7.4 Single-Ended Interfaces
      1. 7.4.1 General Routing Guidelines
      2. 7.4.2 QSPI Board Design and Layout Guidelines
        1. 7.4.2.1 If QSPI is operated in Mode 0 (POL=0, PHA=0):
        2. 7.4.2.2 If QSPI is operated in Mode 3 (POL=1, PHA=1):
    5. 7.5 Differential Interfaces
      1. 7.5.1 General Routing Guidelines
    6. 7.6 Clock Routing Guidelines
      1. 7.6.1 Oscillator Ground Connection
    7. 7.7 DDR2 Board Design and Layout Guidelines
      1. 7.7.1 DDR2 General Board Layout Guidelines
      2. 7.7.2 DDR2 Board Design and Layout Guidelines
        1. 7.7.2.1 Board Designs
        2. 7.7.2.2 DDR2 Interface
          1. 7.7.2.2.1  DDR2 Interface Schematic
          2. 7.7.2.2.2  Compatible JEDEC DDR2 Devices
          3. 7.7.2.2.3  PCB Stackup
          4. 7.7.2.2.4  Placement
          5. 7.7.2.2.5  DDR2 Keepout Region
          6. 7.7.2.2.6  Bulk Bypass Capacitors
          7. 7.7.2.2.7  High Speed Bypass Capacitors
          8. 7.7.2.2.8  Net Classes
          9. 7.7.2.2.9  DDR2 Signal Termination
          10. 7.7.2.2.10 VREF Routing
        3. 7.7.2.3 DDR2 CK and ADDR_CTRL Routing
    8. 7.8 DDR3 Board Design and Layout Guidelines
      1. 7.8.1 DDR3 General Board Layout Guidelines
      2. 7.8.2 DDR3 Board Design and Layout Guidelines
        1. 7.8.2.1  Board Designs
        2. 7.8.2.2  DDR3 Device Combinations
        3. 7.8.2.3  DDR3 Interface Schematic
          1. 7.8.2.3.1 32-Bit DDR3 Interface
          2. 7.8.2.3.2 16-Bit DDR3 Interface
        4. 7.8.2.4  Compatible JEDEC DDR3 Devices
        5. 7.8.2.5  PCB Stackup
        6. 7.8.2.6  Placement
        7. 7.8.2.7  DDR3 Keepout Region
        8. 7.8.2.8  Bulk Bypass Capacitors
        9. 7.8.2.9  High Speed Bypass Capacitors
          1. 7.8.2.9.1 Return Current Bypass Capacitors
        10. 7.8.2.10 Net Classes
        11. 7.8.2.11 DDR3 Signal Termination
        12. 7.8.2.12 VTT
        13. 7.8.2.13 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.8.2.13.1 Three DDR3 Devices
            1. 7.8.2.13.1.1 CK and ADDR_CTRL Topologies, Three DDR3 Devices
            2. 7.8.2.13.1.2 CK and ADDR_CTRL Routing, Three DDR3 Devices
          2. 7.8.2.13.2 Two DDR3 Devices
            1. 7.8.2.13.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.8.2.13.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.8.2.13.3 One DDR3 Device
            1. 7.8.2.13.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.8.2.13.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        14. 7.8.2.14 Data Topologies and Routing Definition
          1. 7.8.2.14.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.8.2.14.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        15. 7.8.2.15 Routing Specification
          1. 7.8.2.15.1 CK and ADDR_CTRL Routing Specification
          2. 7.8.2.15.2 DQS and DQ Routing Specification
    9. 7.9 CVIDEO/SD-DAC Guidelines and Electrical Data/Timing
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABF|367
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Power Supply Sequences

This section describes the power-up and power-down sequence required to ensure proper device operation.

Figure 5-4 through Figure 5-8, and associated notes describes the device Recommended Power Sequencing.

DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788 SPRS916_ELCH_01.gifFigure 5-4 Power-Up Sequencing
  1. Grey shaded areas are windows where it is valid to ramp-up a voltage rail.
  2. Blue dashed lines are not valid windows but show alternate ramp-up possibilities based on whether I/O voltage levels are 1.8V or 3.3V (see associated note for more details).
  3. vdds18v_* and vdda_* rails should not be combined for best performance to avoid transient switching noise impacts on analog domains. vdda_* should not ramp-up before vdds18v_* but could ramp concurrently if design ensures final operational voltage will not be reached until after vdds18v. The preferred sequence is to follow all vdds18v_* to ensure circuit components and PCB design do not cause an inadvertent violation.
  4. vdds_ddr* should not ramp-up before vdds18v_*. The preferred sequence is to follow all vdds18v_* to ensure circuit components and PCB design do not cause an inadvertent violation. vdds_ddr* can ramp-up before, concurrently or after vdda_*, there are no dependencies between vdds_ddr* and vdda_* domains.
    • vdds_ddr* supplies can be combined with vdds18v_* and vdds18v_ddr supplies for DDR2 mode of operation (1.8V) and ramped up together for simplified power sequencing.
    • If vdds18v_ddr and vdds_ddr* are kept separate from vdds18v_* on board, then this combined DDR supply can come up together or after the vdds18v_* supply. The DDR supply in this case should never ramp up before the vdds18v_*.
  5. vdd should not ramp-up before vdds18v_* or vdds_ddr* domains.
  6. vdd_dspeve must not exceed vdd core supply and maintain at least 150mV lower voltage on vdd_dspeve vs vdd. vdd_dspeve could ramp concurrently with vdd if design ensures final operational voltage will not be reached until after vdd and maintains minimum of 150mV less than vdd during entire ramp time. The preferred sequence is to follow vdd to ensure circuit components and PCB design do not cause an inadvertent violation.
  7. If any of the vddshv[1-6] power rails are used for 1.8V I/O signaling, then these rails can be combined with vdds18v_*.
    If 3.3V I/O signaling is required, then these rails must be the last to ramp following vdd_dspeve.
  8. resetn and porz must remain asserted low for a minimum of 12P(12) after xi_osc0 is stable at a valid frequency.
  9. Setup time: SYSBOOT[15:0] pins must be valid 2P(12) before porz is de-asserted high.
  10. Hold time: SYSBOOT[15:0] pins must be valid 15P(12) after porz is de-asserted high.
  11. resetn to rstoutn delay is 2ms.
  12. P = 1/(SYS_CLK1/610) frequency in ns.
  13. Ramped Up is defined as reaching the minimum operational voltage level for the corresponding power domain. For information about voltage levels, refer to , Recommended Operating Conditions.

DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788 SPRS916_ELCH_02.gifFigure 5-5 Recommended Power-Down Sequencing
  1. T1 ≥ 100 µs; T2 = 500 µs; T3 = 1.0 ms; T4 = 1.5ms; V1 = 2.7 V. All "Tn" markers are intended to show total elapsed time, not interval times.
  2. Terminology:
    • VOPR MIN = Minimum Operational Voltage level that ensures device functionality and specified performance in Section 5.4, Recommended Operating Conditions.
    • VOFF = OFF Voltage level is defined to be less than 0.6 V where any current draw has no impact to POH.
    • Ramp Down = transition time from VOPR MIN to VOFF and is slew rate independent.
  3. General timing diagram items:
    • Grey shaded areas show valid transition times for supplies between VOPR MIN and VOFF.
    • Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
    • Dashed vertical lines show approximate elapse times based upon TI recommended PMIC power-down sequencer circuit performance.
  4. porz must be asserted low for 100 µs min to ensure SoC is set to a safe functional state before any voltage begins to ramp down.
  5. vddshv[1-6] domains supplied by 3.3 V:
    • must remain greater than 2.7 V to enable Dual Voltage GPIO selector circuit operation for 100 µs min after porz is asserted low.
    • must be in first group of supplies ramping down after porz has been asserted low for 100 µs min.
    • must not exceed vdds18v by more than 2 V during ramp down, see Figure 5-6, "vdds18v versus vddshv[1-6] Discharge Relationship".
  6. vddshv[1-6] domains supplied by 1.8 V must ramp down concurrently with vdds18v and be sourced from common vdds18v supply.
  7. vdd_dspeve domain can ramp down before or concurrently with vdd.
  8. vdd must ramp down after or concurrently with vdd_dspeve.
  9. vdds_ddr[1-3] domains:
    • should ramp down after vdd begins ramping down.
    • If DDR2 memory is used (requiring 1.8V supply),
      • then vdds_ddr[1-3] can be combined with vdds18v and vdds18v_ddr[1-3] domains and sourced from a common supply. Accordingly, all domains can ramp down concurrently with vdds18v.
      • if vdds_ddr[1-3] and vdds18v_ddr[1-3] are combined but kept separate from vdds18v, then the combined 1.8V DDR supply can ramp down before or concurrently with vdds18v.
  10. vdda_* domains:
    • can ramp down before, concurrently or after vdds_ddr[1-3], there is no dependency between these supplies.
    • can ramp down before or concurrently with vdds18v.
    • must satisfy the vdds18v versus vdda_* discharge relationship (see Figure 5-8) if any of the vdda_* disable point is later or discharge rate is slower than vdds18v.
  11. vdds18v domain:
    • should maintain VOPR MIN (VNOM -5% = 1.71 V) until all other supplies start to ramp down.
    • must satisfy the vdds18v versus vddshv[1-6] discharge relationship (see Figure 5-6) if any of the vddshv[1-6] is operating at 3.3 V.
    • must satisfy the vdds18v versus vdds_ddr[1-3] discharge relationship ( see Figure 5-7) if vdds_ddr[1-3] discharge rate is slower than vdds18v.

Figure 5-6 describes vddshv[1-6] supplies falling before vdds18v supplies delta.

DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788 SPRS916_ELCH_03.gifFigure 5-6 vdds18v versus vddshv[1-6] Discharge Relationship
  1. Vdelta MAX = 2V

If vdds18v and vdds_ddr* are disabled at the same time due to a loss of input power event or if vdds_ddr* discharges more slowly than vdds18v, analysis has shown no reliability impacts when the elapsed time period beginning with vdds18v dropping below 1.0 V and ending with vdds_ddr* dropping below 0.6 V is less than 10 ms (Figure 5-7).

DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788 SPRS916_ELCH_04.gifFigure 5-7 vdds18v and vdds_ddr* Discharge Relationship(1)
  1. V1 > 1.0 V; V2 < 0.6 V; T1 < 10ms.
DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788 SPRS916_ELCH_05.gifFigure 5-8 vdds18v and vdda_* Discharge Relationship(3)
  1. vdda_* can be ≥ vdds18v, until vdds18v drops below 1.62 V.
  2. vdds18v must be ≥ vdda_*, until vdds18v reaches 0.6 V.
  3. V1 = 1.62 V; V2 < 0.6 V.

Figure 5-6 through Figure 5-9 and associated notes described the device Abrupt Power Down Sequence.

A ”loss of input power event” occurs when the system’s input power is unexpectedly removed. Normally, the recommended power-down sequence should be followed and can be accomplished within 1.5-2 ms of elapsed time. This is the typical range of elapsed time available following a loss of power event, see Section 7.3.7, Loss of Input Power Event for design recommendations. If sufficient elapse time is not provided, then an “abrupt” power-down sequence can be supported without impacting POH reliability if all of the following conditions are met (Figure 5-9).

DRA780 DRA781 DRA782 DRA783 DRA784 DRA785 DRA786 DRA787 DRA788 SPRS916_ELCH_06.gifFigure 5-9 Abrupt Power-Down Sequencing(1)
  1. V1 = 2.7 V; V2 = 3.3 V; V3 = 2.0 V; V4 = V5 = V6 = 0.6 V; V7 = V8 = 1.62 V; V9 = 1.3 V; V10 = 1.0 V; V11 = 0.0 V; Tdelta1 > 100 µs; Tdelta2 < 10 ms.
  2. Terminology:
    • VOPR MIN = Minimum Operational Voltage level that ensures device functionality and specified performance in Section 5.4, Recommended Operating Conditions.
    • VOFF = OFF Voltage level is defined to be less than 0.6 V, where any current draw has no impact to POH.
    • Ramp Down = transition time from VOPR MIN to VOFF and is slew rate independent.
  3. General timing diagram items:
    • Grey shaded areas show valid transition times for supplies between VOPR MIN and VOFF.
    • Dashed vertical lines show approximate elapse times based upon TI recommended PMIC power-down sequencer circuit performance.
  4. porz must be asserted low for 100 µs min to ensure SoC is set to a safe functional state before any voltage begins to ramp down.
  5. vddshv[1-6] domains supplied by 3.3 V:
    • must remain greater than 2.7 V to enable Dual Voltage GPIO selector circuit operation for 100µs min, after porz is asserted low.
    • must not exceed vdds18v voltage level by more than 2V during ramp down, until vdds18v drops below VOFF (0.6 V).
  6. vddshv[1-6] domains supplied by 1.8 V must ramp down concurrently with vdds18v and be sourced from common vdds18v supply.
  7. vdd_dspeve, vdd, vdds_ddr[1-3], vdda_* domains can all start to ramp down in any order after 100 µs low assertion of porz.
  8. vdds_ddr* domains:
    • can remain at VOPR MIN or a level greater than vdds18v during ramp down.
    • elapsed time from vdds18v dropping below 1.0 V to vdds_ddr[1-3] dropping below 0.6 V must not exceed 10 ms.
  9. vdda_* domains:
    • can start to ramp down before or concurrently with vdds18v.
    • must not exceed vdds18v voltage level after vdds18v drops below 1.62 V until vdds18v drops below VOFF (0.6 V).
  10. vdds18v domain should maintain a minimum level of 1.62 V (VNOM – 10%) until vdd_dspeve and vdd start to ramp down.