SLVSFF3C December   2021  – October 2022 DRV8328

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specification
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings Comm
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information 1pkg
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Three BLDC Gate Drivers
        1. 8.3.1.1 PWM Control Modes
          1. 8.3.1.1.1 6x PWM Mode
          2. 8.3.1.1.2 3x PWM Mode
        2. 8.3.1.2 Device Hardware Interface
        3. 8.3.1.3 Gate Drive Architecture
          1. 8.3.1.3.1 Propagation Delay
          2. 8.3.1.3.2 Deadtime and Cross-Conduction Prevention
      2. 8.3.2 AVDD Linear Voltage Regulator
      3. 8.3.3 Pin Diagrams
      4. 8.3.4 Gate Driver Shutdown Sequence (DRVOFF)
      5. 8.3.5 Gate Driver Protective Circuits
        1. 8.3.5.1 PVDD Supply Undervoltage Lockout (PVDD_UV)
        2. 8.3.5.2 AVDD Power on Reset (AVDD_POR)
        3. 8.3.5.3 GVDD Undervoltage Lockout (GVDD_UV)
        4. 8.3.5.4 BST Undervoltage Lockout (BST_UV)
        5. 8.3.5.5 MOSFET VDS Overcurrent Protection (VDS_OCP)
        6. 8.3.5.6 VSENSE Overcurrent Protection (SEN_OCP)
        7. 8.3.5.7 Thermal Shutdown (OTSD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Gate Driver Functional Modes
        1. 8.4.1.1 Sleep Mode
        2. 8.4.1.2 Operating Mode
        3. 8.4.1.3 Fault Reset (nSLEEP Reset Pulse)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Three Phase Brushless-DC Motor Control
        1. 9.2.1.1 Detailed Design Procedure
          1. 9.2.1.1.1 Motor Voltage
          2. 9.2.1.1.2 Bootstrap Capacitor and GVDD Capacitor Selection
          3. 9.2.1.1.3 Gate Drive Current
          4. 9.2.1.1.4 Gate Resistor Selection
          5. 9.2.1.1.5 System Considerations in High Power Designs
            1. 9.2.1.1.5.1 Capacitor Voltage Ratings
            2. 9.2.1.1.5.2 External Power Stage Components
            3. 9.2.1.1.5.3 Parallel MOSFET Configuration
          6. 9.2.1.1.6 Dead Time Resistor Selection
          7. 9.2.1.1.7 VDSLVL Selection
          8. 9.2.1.1.8 AVDD Power Losses
          9. 9.2.1.1.9 Power Dissipation and Junction Temperature Losses
      2. 9.2.2 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance Sizing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
      1. 11.3.1 Power Dissipation
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Community Resources
    6. 12.6 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
9.2.1.1.7 VDSLVL Selection

VDSLVL is an analog voltage used to directly set the VDS overcurrent threshold for overcurrent protection. It can be sourced directly from an analog voltage source (such as a digital-to-analog converter) or divided down from a voltage rail (such as a resistor divider from AVDD) as shown in Figure 9-7.

Figure 9-7 Resistor divider to set VDSLVL from a voltage rail

Equation 9 and Equation 10 can be used to set the required VDSLVL voltage using a resistor divider from a voltage source to establish an overcurrent limit given the RDS,on of the MOSFETs used:

Equation 9. VVDSLVL=IOC×Rds(on)
Equation 10. R1R2=VinVVDSLVL-1

where:

  • VVDSLVL = VDSLVL voltage

  • IOCP = VDS overcurrent limit

  • RDS,on = MOSFET on-resistance

  • VIN = voltage source for VDSLVL voltage divider

  • R1/R2 = resistor ratio for setting VDSLVL

For example, if a resistor divider from AVDD is used to set an overcurrent trip threshold of 30-A and the MOSFET RDS(ON) = 10mΩ, then VDSLVL = 0.3V.

In some applications, there will be a difference between battery voltage (VBAT) to directly drive motor power and PVDD voltage to power the DRV8328. Because high-side VDS monitoring is referenced from PVDD-SHx, VDSLVL needs to be selected appropriately to accommodate for the difference in VBAT and PVDD.

Equation 11 helps select an appropriate VDSLVL if there is a difference between PVDD and VDSLVL:

Equation 11. VDSLVL=(VBAT-PVDD)+IOC*RDS(ON)

For instance, if VBAT = 24.0 V, PVDD = 23.3 V, Rdson = 10-mΩ, and I_OC = 30-A, then VDSLVL should equal 1.0V to detect a 30-A overcurrent event across the high-side FET and a 100-A overcurrent event across the low-side FET.