SLVSFF3C December   2021  – October 2022 DRV8328

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specification
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings Comm
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information 1pkg
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Three BLDC Gate Drivers
        1. 8.3.1.1 PWM Control Modes
          1. 8.3.1.1.1 6x PWM Mode
          2. 8.3.1.1.2 3x PWM Mode
        2. 8.3.1.2 Device Hardware Interface
        3. 8.3.1.3 Gate Drive Architecture
          1. 8.3.1.3.1 Propagation Delay
          2. 8.3.1.3.2 Deadtime and Cross-Conduction Prevention
      2. 8.3.2 AVDD Linear Voltage Regulator
      3. 8.3.3 Pin Diagrams
      4. 8.3.4 Gate Driver Shutdown Sequence (DRVOFF)
      5. 8.3.5 Gate Driver Protective Circuits
        1. 8.3.5.1 PVDD Supply Undervoltage Lockout (PVDD_UV)
        2. 8.3.5.2 AVDD Power on Reset (AVDD_POR)
        3. 8.3.5.3 GVDD Undervoltage Lockout (GVDD_UV)
        4. 8.3.5.4 BST Undervoltage Lockout (BST_UV)
        5. 8.3.5.5 MOSFET VDS Overcurrent Protection (VDS_OCP)
        6. 8.3.5.6 VSENSE Overcurrent Protection (SEN_OCP)
        7. 8.3.5.7 Thermal Shutdown (OTSD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Gate Driver Functional Modes
        1. 8.4.1.1 Sleep Mode
        2. 8.4.1.2 Operating Mode
        3. 8.4.1.3 Fault Reset (nSLEEP Reset Pulse)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Three Phase Brushless-DC Motor Control
        1. 9.2.1.1 Detailed Design Procedure
          1. 9.2.1.1.1 Motor Voltage
          2. 9.2.1.1.2 Bootstrap Capacitor and GVDD Capacitor Selection
          3. 9.2.1.1.3 Gate Drive Current
          4. 9.2.1.1.4 Gate Resistor Selection
          5. 9.2.1.1.5 System Considerations in High Power Designs
            1. 9.2.1.1.5.1 Capacitor Voltage Ratings
            2. 9.2.1.1.5.2 External Power Stage Components
            3. 9.2.1.1.5.3 Parallel MOSFET Configuration
          6. 9.2.1.1.6 Dead Time Resistor Selection
          7. 9.2.1.1.7 VDSLVL Selection
          8. 9.2.1.1.8 AVDD Power Losses
          9. 9.2.1.1.9 Power Dissipation and Junction Temperature Losses
      2. 9.2.2 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance Sizing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
      1. 11.3.1 Power Dissipation
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Community Resources
    6. 12.6 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1 Absolute Maximum Ratings

over operating temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Power supply pin voltage PVDD -0.3 65 V
Bootstrap pin voltage BSTx -0.3 80 V
Bootstrap pin voltage BSTx with respect to SHx   -0.3 20 V
Bootstrap pin voltage BSTx with respect to GHx   -0.3 20 V
Charge pump pin voltage CPL, CPH -0.3 VGVDD V
Gate driver regulator pin voltage GVDD -0.3 20 V
Analog regulator pin voltage AVDD -0.3 4 V
Logic pin voltage (nSLEEP) nSLEEP -0.3 65 V
Logic pin voltage DRVOFF, DT, INHx, INLx, nFAULT, VDSLVL -0.3 6 V
High-side gate drive pin voltage GHx -8 80 V
Transient 500-ns high-side gate drive pin voltage GHx -10 80 V
High-side gate drive pin voltage GHx with respect to SHx -0.3 20 V
High-side source pin voltage SHx -8 70 V
Transient 500-ns high-side source pin voltage  SHx -10 72 V
Low-side gate drive pin voltage GLx with respect to LSS -0.3 20 V
Transient 500-ns low-side gate drive pin voltage(2) GLx with respect to LSS -1 20 V
Low-side gate drive pin voltage GLx with respect to GVDD 0.3 V
Transient 500-ns low-side gate drive pin voltage GLx with respect to GVDD 1 V
Low-side source sense pin voltage LSS -1 1 V
Transient 500-ns low-side source sense pin voltage LSS -10 8 V
Gate drive current GHx, GLx Internally Limited Internally Limited A
Current sense amplifer reference input pin voltage CSAREF -0.3 5.5 V
Shunt amplifier input pin voltage SN, SP -1 1 V
Transient 500-ns shunt amplifier input pin voltage SN, SP -10 8 V
Shunt amplifier output pin voltage SO -0.3 VCSAREF + 0.3 V
Junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime
(2) Supports upto 5A for 500 nS when GLx-LSS is negative