SLVSFF3C December   2021  – October 2022 DRV8328

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specification
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings Comm
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information 1pkg
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Three BLDC Gate Drivers
        1. 8.3.1.1 PWM Control Modes
          1. 8.3.1.1.1 6x PWM Mode
          2. 8.3.1.1.2 3x PWM Mode
        2. 8.3.1.2 Device Hardware Interface
        3. 8.3.1.3 Gate Drive Architecture
          1. 8.3.1.3.1 Propagation Delay
          2. 8.3.1.3.2 Deadtime and Cross-Conduction Prevention
      2. 8.3.2 AVDD Linear Voltage Regulator
      3. 8.3.3 Pin Diagrams
      4. 8.3.4 Gate Driver Shutdown Sequence (DRVOFF)
      5. 8.3.5 Gate Driver Protective Circuits
        1. 8.3.5.1 PVDD Supply Undervoltage Lockout (PVDD_UV)
        2. 8.3.5.2 AVDD Power on Reset (AVDD_POR)
        3. 8.3.5.3 GVDD Undervoltage Lockout (GVDD_UV)
        4. 8.3.5.4 BST Undervoltage Lockout (BST_UV)
        5. 8.3.5.5 MOSFET VDS Overcurrent Protection (VDS_OCP)
        6. 8.3.5.6 VSENSE Overcurrent Protection (SEN_OCP)
        7. 8.3.5.7 Thermal Shutdown (OTSD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Gate Driver Functional Modes
        1. 8.4.1.1 Sleep Mode
        2. 8.4.1.2 Operating Mode
        3. 8.4.1.3 Fault Reset (nSLEEP Reset Pulse)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Three Phase Brushless-DC Motor Control
        1. 9.2.1.1 Detailed Design Procedure
          1. 9.2.1.1.1 Motor Voltage
          2. 9.2.1.1.2 Bootstrap Capacitor and GVDD Capacitor Selection
          3. 9.2.1.1.3 Gate Drive Current
          4. 9.2.1.1.4 Gate Resistor Selection
          5. 9.2.1.1.5 System Considerations in High Power Designs
            1. 9.2.1.1.5.1 Capacitor Voltage Ratings
            2. 9.2.1.1.5.2 External Power Stage Components
            3. 9.2.1.1.5.3 Parallel MOSFET Configuration
          6. 9.2.1.1.6 Dead Time Resistor Selection
          7. 9.2.1.1.7 VDSLVL Selection
          8. 9.2.1.1.8 AVDD Power Losses
          9. 9.2.1.1.9 Power Dissipation and Junction Temperature Losses
      2. 9.2.2 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance Sizing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
      1. 11.3.1 Power Dissipation
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Community Resources
    6. 12.6 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

4.5 V ≤ VPVDD ≤ 60 V, –40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for TA = 25°C, VPVDD = 24 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (AVDD, PVDD, GVDD)
IPVDDQ PVDD sleep mode current VPVDD =24V, nSLEEP = 0, TA = 25°C 1 µA
nSLEEP = LOW 2 µA
IPVDDS PVDD standby mode current VPVDD = 24 V;  nSLEEP = HIGH, INHx = INLX = LOW, DRVOFF = HIGH 2 4 mA
 nSLEEP = HIGH, INHx = INLX = LOW, DRVOFF = HIGH 3 5.5 mA
IPVDD PVDD active mode current VPVDD = 24 V, nSLEEP = HIGH, INHx = INLX = Switching@20kHz, No FETs connected 4 7 mA
nSLEEP = HIGH, INHx = INLX = Switching@20kHz, No FETs connected 5 10 mA
VPVDD = 8 V, nSLEEP = HIGH, INHx = INLX = LOW, No FETs connected 5 10 mA
VPVDD = 24 V, nSLEEP = HIGH, INHx = INLX = LOW, No FETs connected 5 7 mA
ILBSx Bootstrap pin leakage current VBSTx = VSHx = 60V, VGVDD = 0V, nSLEEP = LOW 5 10 16 µA
ILBS_TRAN Bootstrap pin active mode transient leakage current  INLx = INHx = Switching@20kHz, No FETs connected 60 115 300 µA
ILBS_DC_SRC Bootstrap pin active mode leakage static source current INHx = HIGH, INLx = LOW, INLy = INLz = HIGH, nSLEEP = HIGH, VPVDD = VSHX = VGVDD = 12V, VBSTx - VSHx = 5V 135 200 280 µA
INHx = HIGH, INLx = LOW, INLy = INLz = HIGH, nSLEEP = HIGH, VPVDD = VSHX = VGVDD = 12V, VBSTx - VSHx = 7V 70 105 145 µA
INHx = LOW, INLx = LOW, INLy = INLz = HIGH, nSLEEP = HIGH, VPVDD = VSHX = VGVDD = 12V, VBSTx - VSHx = 5V 25 50 90 µA
INHx = LOW, INLx = LOW, INLy = INLz = HIGH, nSLEEP = HIGH, VPVDD = VSHX = VGVDD = 12V, VBSTx - VSHx = 7V 16 28 50 µA
ILBS_DC_SINK Bootstrap pin active mode leakage static sink current INHx = LOW, INLx = LOW, INLy = INLz = HIGH, nSLEEP = HIGH, VPVDD = VSHX = VGVDD = 12V, VBSTx - VSHx = 12V 10 40 90 µA
INHx = High, INLx = LOW, INLy = INLz = HIGH, nSLEEP = HIGH, VPVDD = VSHX = VGVDD = 12V, VBSTx - VSHx = 12V 14 45 91 µA
ILSHx Source pin leakage current  INHx = INLx = LOW, VBSTx - VSHx = 15, VSHx = 0 to 60V, nSLEEP = HIGH, DRVOFF = LOW 80 145 210 µA
INHx = INLx = LOW, VBSTx - VSHx = 11, VSHx = 0 to 60V, nSLEEP = HIGH, DRVOFF = LOW 15 20 30 µA
INHx = High,  INLx = LOW, VBSTx - VSHx = 15, VSHx = 0 to 60V, nSLEEP = HIGH, DRVOFF = LOW 80 145 210 µA
INHx = HIGH,  INLx = LOW, VBSTx - VSHx = 11, VSHx = 0 to 60V, nSLEEP = HIGH, DRVOFF = LOW 13 25 35 µA
tWAKE Turnon time (nSLEEP) nSLEEP = HIGH to Active mode (Outputs Ready), DRVOFF = LOW, CGVDD  = 10 uF, CBSTx = 1 uF  1 2 ms
nSLEEP = High to Active mode (Outputs Ready). CGVDD  = 100 uF, CAVDD  = 10 uF, CBSTx = 10 uF  10 15 ms
VPVDD = 12V, nSLEEP = HIGH to Active mode (Outputs Ready), DRVOFF = LOW, CGVDD  = 10 uF 1 2 ms
Turnon time (DRVOFF) DRVOFF = LOW to Active mode (Outputs Ready), nSLEEP = High 0.05 0.1 ms
tSLEEP Turnoff time nSLEEP = LOW to Sleep mode  20 us
tRST Minimum Reset Pulse Time nSLEEP = LOW period to reset faults 1 1.2 us
VGVDD_RT GVDD Gate driver regulator voltage (Room Temperature) VPVDD ≥ 40 V, IGS  = 10 mA, TJ= 25°C 11.8 13 15 V
22 V ≤VPVDD ≤ 40 V, IGS  = 30 mA, TJ= 25°C 11.8 13 15 V
8 V ≤VPVDD ≤ 22 V, IGS  = 30 mA, TJ= 25°C 11.8 13 15 V
6.75 V ≤VPVDD ≤ 8 V, IGS  = 10 mA, TJ= 25°C 11.8 13 14.5 V
4.5 V ≤VPVDD ≤ 6.75 V, IGS  = 10 mA, TJ= 25°C 2*VPVDD - 1 13.5 V
VGVDD GVDD Gate driver regulator voltage  VPVDD ≥ 40 V, IGS  = 10 mA 11.5 15.5 V
22 V ≤VPVDD ≤ 40 V, IGS  = 30 mA 11.5 15.5 V
8 V ≤VPVDD ≤ 22 V; IGS  = 30 mA 11.5 15.5 V
6.75 V ≤VPVDD ≤ 8 V, IGS  = 10 mA 11.5 14.5 V
4.5 V ≤VPVDD ≤ 6.75 V, IGS  = 10 mA 2*VPVDD - 1.4 13.5 V
VAVDD_RT AVDD Analog regulator voltage (Room Temperature) VPVDD ≥ 6 V, 0 mA ≤ IAVDD ≤ 30 mA, TJ= 25°C 3.26 3.3 3.33 V
VPVDD ≥ 6 V, 30 mA ≤ IAVDD ≤ 80 mA, TJ= 25°C 3.2 3.3 3.4 V
VPVDD ≤ 6 V, 0 mA ≤ IAVDD ≤ 50 mA, TJ= 25°C 3.13 3.3 3.46 V
VAVDD AVDD Analog regulator voltage VPVDD ≥ 6 V, 0 mA ≤ IAVDD ≤ 80 mA  3.2 3.3 3.4 V
VPVDD ≤ 6 V, 0 mA ≤ IAVDD ≤ 50 mA 3.125 3.3 3.5 V
LOGIC-LEVEL INPUTS (DRVOFF, INHx, INLx, nSLEEP etc)
VIL Input logic low voltage DRVOFF  0.8 V
INLx, INHx pins 0.8 V
VIH Input logic high voltage DRVOFF 2.2 V
INLx, INHx pins 2.2 V
VHYS Input hysteresis DRVOFF 200 400 650 mV
INLx, INHx pins 45 240 350 mV
IIL Input logic low current VPIN (Pin Voltage) = 0 V; -1 0 1 µA
IIH Input logic high current nSLEEP, VPIN (Pin Voltage) = 65 V; 3 6.5 10 µA
nSLEEP, VPIN (Pin Voltage) = 5 V; 3 6 10 µA
Other pins, VPIN (Pin Voltage) = 5 V; 7 20 35 µA
RPD_DRVOFF Input pulldown resistance DRVOFF To GND 100 200 300 kΩ
RPD_nSLEEP Input pulldown resistance nSLEEP To GND 500 800 1500 kΩ
RPD Input pulldown resistance All other pins To GND 150 250 350 kΩ
FOUR-LEVEL INPUTS (GAIN)
VL1 Input level 1 voltage Tied to GND 0 0.18*AVDD V
VL2 Input level 2 voltage 50 kΩ +/- 5% tied to GND 0.48*AVDD 0.5*AVDD 0.52*AVDD V
VL3 Input level 3 voltage 200 kΩ +/- 5% tied to GND 0.82*AVDD 0.833*AVDD 0.85*AVDD V
VL4 Input level 4 voltage HiZ or Connect to AVDD AVDD V
RPU Input pullup resistance GAIN To AVDD 80 100 120 kΩ
OPEN-DRAIN OUTPUTS (nFAULT etc)
VOL Output logic low voltage IOD = 5 mA 0.4 V
IOZ Output logic high current VOD = 5 V -1 1 µA
COD Output capacitance VOD = 5 V 30 pF
GATE DRIVERS (GHx, GLx, SHx, SLx)
VGSHx_LO High-side gate drive low level voltage IGLx = -100 mA; VGVDD = 12V; No FETs connected 0.05 0.11 0.24 V
VGSHx_HI High-side gate drive high level voltage (VBSTx - VGHx) IGHx = 100 mA; VGVDD = 12V; No FETs connected 0.28 0.44 0.82 V
VGSLx_LO Low-side gate drive low level voltage IGLx = -100 mA; VGVDD = 12V; No FETs connected 0.05 0.11 0.27 V
VGSLx_HI Low-side gate drive high level voltage (VGVDD - VGHx) IGHx = 100 mA; VGVDD = 12V; No FETs connected 0.28 0.44 0.82 V
VGSH_100_PH High-side gate drive voltage in steady state with 100 % duty cycle (GHx- SHx) INHx = HIGH, INLx = LOW, INLy = INLz = HIGH, VPVDD >15V, VGVDD ≥11.5V 8.4 9.6 11.1 V
INHx = HIGH, INLx = LOW, INLy = INLz = HIGH, VGVDD ≥11.5V 7.5 8.3 9 V
INHx = HIGH, INLx = LOW, INLy = INLz = HIGH, 7V ≥VGVDD ≥ 8V 5.7 6.5 7.6 V
RDS(ON)_PU_HS High-side pullup switch resistance IGHx = 100 mA; VGVDD= 12V 2.7 4.5 8.4 Ω
RDS(ON)_PD_HS High-side pulldown switch resistance IGHx = 100 mA; VGVDD = 12V 0.5 1.1 2.4 Ω
RDS(ON)_PU_LS Low-side pullup switch resistance IGLx = 100 mA; VGVDD = 12V 2.7 4.5 8.3 Ω
RDS(ON)_PD_LS Low-side pulldown switch resistance IGLx = 100 mA; VGVDD = 12V 0.5 1.1 2.8 Ω
IDRIVEP_HS High-side peak source gate current VGSHx = 12V 550 1000 1575 mA
IDRIVEN_HS High-side peak sink gate current VGSHx = 0V 1150 2000 2675 mA
IDRIVEP_LS Low-side peak source gate current VGSLx = 12V 550 1000 1575 mA
IDRIVEN_LS Low-side peak sink gate current VGSLx = 0V 1150 2000 2675 mA
RPD_LS Low-side passive pull down GLx to LSS 80 100 120 kΩ
RPDSA_HS High-side semiactive pull down GHx to SHx, VGSHx = 2V 8 10 12.5 kΩ
GATE DRIVERS TIMINGS
tPDR_LS Low-side rising propagation delay INLx to GLx rising, VGVDD > 8V 70 100 145 ns
tPDF_LS Low-side falling propagation delay INLx to GLx falling, VGVDD > 8V 70 100 135 ns
tPDR_HS High-side rising propagation delay INHx to GHx rising, VGVDD  = VBSTx - VSHx > 8V
 65 100 145 ns
tPDF_HS High-side falling propagation delay INHx to GHx falling, VGVDD = VBSTx - VSHx > 8V
 70 100 140 ns
tPD_MATCH_PH Matching propagation delay per phase GLx turning ON to GLx turning OFF, VGVDD = VBSTx - VSHx > 8V; SHx = 0V to 60V, No load on GHx and GLx -25 ±4 25 ns
GLx turning OFF to GHx turning ON, VGVDD = VBSTx - VSHx > 8V; SHx = 0V to 60V, No load on GHx and GLx -28 ±4 28 ns
GHx turning ON to GHx turning OFF, VGVDD = VBSTx - VSHx > 8V; SHx = 0V to 60V, No load on GHx and GLx -25 ±4 25 ns
GHx turning OFF to GLx turning ON, VGVDD = VBSTx - VSHx > 8V; SHx = 0V to 60V, No load on GHx and GLx -25 ±4 25 ns
tPD_MATCH_PH_PH Matching propagation delay phase to phase GHx turning ON to GHy turning ON, VGVDD = VBSTx - VSHx > 8V; SHx = 0V to 60V, No load on GHx and GLx -10 ±4 10 ns
GLx turning ON to GLy turning ON, VGVDD = VBSTx - VSHx > 8V; SHx = 0V to 60V, No load on GHx and GLx -10 ±4 10 ns
GHx turning OFF to GHy turning OFF, VGVDD = VBSTx - VSHx > 8V; SHx = 0V to 60V, No load on GHx and GLx -15 ±4 15 ns
GLx turning OFF to GLy turning OFF, VGVDD = VBSTx - VSHx > 8V; SHx = 0V to 60V, No load on GHx and GLx -10 ±4 10 ns
tPW_MIN Minimum input pulse width on INHx, INLx that changes the output on GHx, GLx 18 32 45 ns
tDEAD Gate drive dead time configurable range  50 2000 ns
tDEAD Gate drive dead time DT pin floating  35 55 90 ns
DT pin connected to GND 25 55 80 ns
10 kΩ between DT pin and GND 75 100 140 ns
390 kΩ between DT pin and GND 1350 2000 2650 ns
BOOTSTRAP DIODES
VBOOTD Bootstrap diode forward voltage IBOOT = 100 µA 0.8 V
IBOOT = 100 mA 1.6 V
RBOOTD Bootstrap dynamic resistance (ΔVBOOTD/ΔIBOOT) IBOOT = 100 mA and 50 mA 4.5 5.5 9 Ω
CURRENT SHUNT AMPLIFIERS (SNx, SOx, SPx, CSAREF)
ACSA Sense amplifier gain  CSAGAIN = Tied to GND 4.92 5 5.05 V/V
CSAGAIN = 50kΩ ±5% tied to GND 9.9 10 10.1 V/V
CSAGAIN = 200kΩ ±5% tied to GND 19.75 20 20.2 V/V
CSAGAIN =Hi-Z; 39.6 40 40.6 V/V
ACSA_ERR Sense amplifier gain error TJ = 25℃ -1.5 1.5 %
ACSA_ERR_DRIFT Sense amplifier gain error temperature drift -20 20 ppm/℃
NL Non linearity Error 0.01 0.05 %
tSET Settling time to ±1% VSTEP = 1.6 V, ACSA = 5 V/V, CLOAD = 500pF 0.6 1 µs
VSTEP = 1.6 V, ACSA = 10 V/V, CLOAD = 500pF 0.6 1.1 µs
VSTEP = 1.6 V, ACSA = 20 V/V, CLOAD = 500pF 0.7 1.2 µs
VSTEP = 1.6 V, ACSA = 40 V/V, CLOAD = 500pF 0.8 1.7 µs
tSET Settling time to ±1% VSTEP = 1.6 V, ACSA = 5 V/V, CLOAD = 60pF 0.3 0.5 µs
VSTEP = 1.6 V, ACSA = 10 V/V, CLOAD = 60pF 0.3 0.5 µs
VSTEP = 1.6 V, ACSA = 20 V/V, CLOAD = 60pF 0.3 0.65 µs
VSTEP = 1.6 V, ACSA = 40 V/V, CLOAD = 60pF 0.3 0.8 µs
BW Bandwidth ACSA = 5 V/V, CLOAD = 60-pF, small signal -3 dB 3 5 7 MHz
ACSA = 10 V/V, CLOAD = 60-pF, small signal -3 dB 2.5 4.8 6.6 MHz
ACSA = 20 V/V, CLOAD = 60-pF, small signal -3 dB 2 4 5.4 MHz
ACSA = 40 V/V, CLOAD = 60-pF, small signal -3 dB 1.75 3 4.2 MHz
tSR Output slew rate VSTEP = 1.6 V, ACSA = 5 V/V, CLOAD = 60-pF, low to high transition 12 V/µs
VSTEP = 1.6 V, ACSA = 10 V/V, CLOAD = 60-pF, low to high transition 13 V/µs
VSTEP = 1.6 V, ACSA = 20 V/V, CLOAD = 60-pF, low to high transition 11 V/µs
VSTEP = 1.6 V, ACSA = 40 V/V, CLOAD = 60-pF, low to high transition 11 V/µs
VSWING Output voltage range VCSAREF = 3  0.25 2.75 V
VSWING Output voltage range VCSAREF = 5.5 0.25 5.25 V
VSWING Output voltage range VCSAREF = 3 to 5.5 V  0.25 VCSAREF - 0.25 V
VCOM Common-mode input range -0.15 0.15 V
VDIFF Differential-mode input range -0.3 0.3 V
VOFF Input offset voltage VSP = VSN = GND; TJ = -40℃, CSA_VREF = 0 -1.5 1.5 mV
VOFF Input offset voltage VSP = VSN = GND; TJ = 25℃, CSA_VREF = 0 -1.2 1.2 mV
VOFF Input offset voltage VSP = VSN = GND; TJ = 175℃, CSA_VREF= 0 -1.5 1.5 mV
VOFF Input offset voltage VSP = VSN = GND -1.5 1.5 mV
VOFF_DRIFT Input drift offset voltage VSP = VSN = GND 8 10 µV/℃
VBIAS Output voltage bias ratio VSP = VSN = GND 0.122 0.125 0.128 V
VBIAS_ACC Output voltage bias ratio accuracy VSP = VSN = GND -1.2 1.2 %
IBIAS Input bias current VSP = VSN = GND, VCSAREF =  3V to 5.5V 100 µA
IBIAS_OFF Input bias current offset ISP – ISN -1 1 µA
ICSASRC SO ouput sink current capability 5 7 11 mA
ICSASRC SO ouput source current capability 2 3.7 6.6 mA
CMRR Common-mode rejection ratio DC 80 dB
20 kHz 65 dB
PSRR Power-supply rejection ratio (CSAREF) CSAREF to SOx, DC, Differential 80 dB
CSAREF to SOx, 20 kHz, Differential 70 dB
PSRR Power-supply rejection ratio (CSAREF) CSAREF to SOx, 20 kHz, Single Ended 40 dB
ICSA_SUP Supply current for CSA VCSAREF = 3.V to 5.5V 1.5 2.1 mA
TCMREC Common mode recovery time 0.6 0.7 us
CLOAD Maximum load capacitance 10 nF
VOFF_OUT Output offset error  ACSA = 5 V/V -3 3 mV
ACSA = 10 V/V -4 4 mV
ACSA = 20 V/V -5 5 mV
ACSA = 40 V/V -6 6 mV
PROTECTION CIRCUITS
VPVDD_UV PVDD undervoltage lockout threshold VPVDD rising 4.3 4.4 4.5 V
VPVDD falling 4 4.1 4.25
VPVDD_UV_HYS PVDD undervoltagelockout  hysteresis Rising to falling threshold 225 265 325 mV
tPVDD_UV_DG PVDD undervoltage deglitch time 10 20 30 µs
VAVDD_POR AVDD supply POR threshold AVDD rising 2.7 2.85 3.0 V
AVDD falling 2.5 2.65 2.8
VAVDD_POR_HYS AVDD POR hysteresis Rising to falling threshold 170 200 250 mV
tAVDD_POR_DG AVDD POR deglitch time 7 12 22 µs
VGVDD_UV GVDD undervoltage threshold VGVDD rising 7.3 7.5 7.8 V
VGVDD falling 6.4 6.7 6.9 V
VGVDD_UV_HYS GVDD undervoltage hysteresis Rising to falling threshold 800 900 1000 mV
tGVDD_UV_DG GVDD undervoltage deglitch time 5 10 15 µs
VBST_UV Bootstrap undervoltage threshold VBSTx- VSHx; VBSTx rising 3.9 4.45 5 V
VBSTx- VSHx; VBSTx falling 3.7 4.2 4.8 V
VBST_UV_HYS Bootstrap undervoltage hysteresis Rising to falling threshold 150 220 285 mV
tBST_UV_DG Bootstrap undervoltage deglitch time 2 4 6 µs
VDS_LVL_RNG VDS overcurrent protection threshold linear range  0.1 2.5 V
VDS_DIS VDS overcurrent protection disable resistor  VDSLVL pin to GVDD 70 100 500 kΩ
VDS_LVL VDS overcurrent protection threshold Reference VDSLVL = 100 kΩ to GVDD 3 4.2 5.5 V
VDSLVL = 0.1V 0.065 0.1 0.145 V
VDSLVL pin = 2.5V 2.2 2.5 2.8
VSENSE_LVL VSENSE overcurrent protection threshold LSS to GND pin = 0.5V 0.48 0.5 0.52 V
tDS_BLK VDS overcurrent protection blanking time  0.5 1 2.7 µs
tDS_DG VDS and VSENSE overcurrent protection deglitch time  1.5 3 5 µs
tSD_SINK_DIG DRVOFF peak sink current duration 3 5 7 µs
tSD_DIG DRVOFF digital shutdown delay 0.5 1.5 2.2 µs
tSD DRVOFF analog shutdown delay 7 14 21 µs
TOTSD Thermal shutdown temperature TJ rising;   160 170 187 °C
THYS Thermal shutdown hysteresis 16 20 23 °C