SLVSI02 May   2025 DRV8376-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 SPI Slave Mode Timings
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Output Stage
      2. 7.3.2  Control Modes
        1. 7.3.2.1 6x PWM Mode (PWM_MODE = 00b or 01b or MODE_SR Pin Tied to AGND or in Hi-Z)
        2. 7.3.2.2 3x PWM Mode (PWM_MODE = 10b or 11b or MODE_SR Pin is Connected to GVDD or to GVDD with RMODE)
      3. 7.3.3  Device Interface Modes
        1. 7.3.3.1 Serial Peripheral Interface (SPI)
        2. 7.3.3.2 Hardware Interface
      4. 7.3.4  AVDD and GVDD Linear Voltage Regulator
      5. 7.3.5  Charge Pump
      6. 7.3.6  Slew Rate Control
      7. 7.3.7  Cross Conduction (Dead Time)
      8. 7.3.8  Propagation Delay
      9. 7.3.9  Pin Diagrams
        1. 7.3.9.1 Logic Level Input Pin (Internal Pulldown)
        2. 7.3.9.2 Logic Level Input Pin (Internal Pullup)
        3. 7.3.9.3 Open Drain Pin
        4. 7.3.9.4 Push Pull Pin
        5. 7.3.9.5 Four Level Input Pin
      10. 7.3.10 Current Sense Amplifiers
        1. 7.3.10.1 Current Sense Amplifier Operation
      11. 7.3.11 Active Demagnetization
        1. 7.3.11.1 Automatic Synchronous Rectification Mode (ASR Mode)
          1. 7.3.11.1.1 Automatic Synchronous Rectification in Commutation
          2. 7.3.11.1.2 Automatic Synchronous Rectification in PWM Mode
        2. 7.3.11.2 Automatic Asynchronous Rectification Mode (AAR Mode)
      12. 7.3.12 Cycle-by-Cycle Current Limit
        1. 7.3.12.1 Cycle by Cycle Current Limit with 100% Duty Cycle Input
      13. 7.3.13 Protections
        1. 7.3.13.1 VM Supply Undervoltage Lockout (RESET)
        2. 7.3.13.2 AVDD Undervoltage Protection (AVDD_UV)
        3. 7.3.13.3 GVDD Undervoltage Lockout (GVDD_UV)
        4. 7.3.13.4 VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 7.3.13.5 Overvoltage Protections (OV)
        6. 7.3.13.6 Overcurrent Protection (OCP)
          1. 7.3.13.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.13.6.2 OCP Automatic Retry (OCP_MODE = 01b)
          3. 7.3.13.6.3 OCP Report Only (OCP_MODE = 10b)
          4. 7.3.13.6.4 OCP Disabled (OCP_MODE = 11b)
        7. 7.3.13.7 Thermal Warning (OTW)
        8. 7.3.13.8 Thermal Shutdown (OTS)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Operating Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT or nSLEEP Reset Pulse)
      2. 7.4.2 DRVOFF Functionality
    5. 7.5 SPI Communication
      1. 7.5.1 Programming
        1. 7.5.1.1 SPI Format
  9. 8 Register Map
    1. 8.1 STATUS Registers
    2. 8.2 CONTROL Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Three-Phase Brushless-DC Motor Control
        1. 9.2.1.1 Detailed Design Procedure
          1. 9.2.1.1.1 Motor Voltage
          2. 9.2.1.1.2 Using Active Demagnetization
          3. 9.2.1.1.3 Current Limit Implementation
          4. 9.2.1.1.4 Current Sensing and Output Filtering
          5. 9.2.1.1.5 Power Dissipation and Junction Temperature Losses
        2. 9.2.1.2 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Bulk Capacitance
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
      3. 9.4.3 Thermal Considerations
        1. 9.4.3.1 Power Dissipation
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.13 Protections

The DRV8376-Q1 family of devices is protected against VM undervoltage, charge pump undervoltage, and overcurrent events. Table 7-5 summarizes various faults details.

Table 7-5 Fault Action and Response (SPI Devices)
FAULT CONDITION CONFIGURATION REPORT H-BRIDGE LOGIC RECOVERY
VM undervoltage
(RESET)		 VVM < VUVLO — — Hi-Z Disabled Automatic:
VVM > VUVLO_R
CLR_FLT, nSLEEP Reset Pulse (RESET bit)
GVDD undervoltage
(RESET)		 VGVDD < VGVDD_UV — — Hi-Z Disabled Automatic:
VGVDD > VGVDD_UV_R
CLR_FLT, nSLEEP Reset Pulse (RESET bit)
AVDD undervoltage
(RESET)		 VAVDD < VAVDD_UV — — Hi-Z Disabled Automatic:
VAVDD > VAVDD_UV_R
CLR_FLT, nSLEEP Reset Pulse (RESET bit)
Charge pump undervoltage
(VCP_UV)		 VCP < VCPUV — nFAULT Hi-Z Active Automatic:
VVCP > VCPUV
CLR_FLT, nSLEEP Reset Pulse (VCP_UV bit)
OverVoltage Protection
(OVP)		 VVM > VOVP OVP_MODE = 0b None Active Active No action (OVP Disabled)
OVP_MODE = 1b FAULT Hi-Z Active Automatic:
VVM < VOVP
CLR_FLT, nSLEEP Reset Pulse (OVP bit)
Overcurrent Protection
(OCP)		 IPHASE > IOCP OCP_MODE = 00b nFAULT Hi-Z Active Latched:
CLR_FLT, nSLEEP Reset Pulse (OCP bits)
OCP_MODE = 01b nFAULT Hi-Z Active Retry:
tRETRY
CLR_FLT, nSLEEP Reset Pulse (OCP bits)
OCP_MODE = 10b nFAULT Active Active Report only:
CLR_FLT, nSLEEP Reset Pulse (OCP bits)
OCP_MODE = 11b None Active Active No action
ILIMIT VILIMIT > VSO ILIMFLT_MODE = 0b None ILIMIT Mode Active Automatic:
High side on the next rising edge of INHx
Low side on the next rising edge of INLx
ILIMFLT_MODE = 1b nFAULT ILIMIT Mode Active Automatic:
High side on the next rising edge of INHx
Low side on the next rising edge of INLx
SPI Error
(SPI_FLT)		 SCLK, Parity and ADDR fault SPIFLT_MODE = 0b None Active Active No action
SPIFLT_MODE = 1b nFAULT Active Active Report only:
CLR_FLT, nSLEEP Reset Pulse (SPI_FLT bit)
OTP Error
(OTP_ERR)		 OTP reading is erroneous — nFAULT Hi-Z Active Latched:
Power Cycle, CLR_FLT
Thermal warning
(OTW)		 TJ > TOTW OTW_MODE = 0b None Active Active No action
OTW_MODE = 1b nFAULT Active Active Automatic:
TJ < TOTW – TOTW_HYS
CLR_FLT, nSLEEP Pulse (OTW bit)
Thermal shutdown
(OTSD)		 TJ > TTSD — nFAULT Hi-Z Active Automatic:
TJ < TTSD – TTSD_HYS