SLVSI02 May   2025 DRV8376-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 SPI Slave Mode Timings
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Output Stage
      2. 7.3.2  Control Modes
        1. 7.3.2.1 6x PWM Mode (PWM_MODE = 00b or 01b or MODE_SR Pin Tied to AGND or in Hi-Z)
        2. 7.3.2.2 3x PWM Mode (PWM_MODE = 10b or 11b or MODE_SR Pin is Connected to GVDD or to GVDD with RMODE)
      3. 7.3.3  Device Interface Modes
        1. 7.3.3.1 Serial Peripheral Interface (SPI)
        2. 7.3.3.2 Hardware Interface
      4. 7.3.4  AVDD and GVDD Linear Voltage Regulator
      5. 7.3.5  Charge Pump
      6. 7.3.6  Slew Rate Control
      7. 7.3.7  Cross Conduction (Dead Time)
      8. 7.3.8  Propagation Delay
      9. 7.3.9  Pin Diagrams
        1. 7.3.9.1 Logic Level Input Pin (Internal Pulldown)
        2. 7.3.9.2 Logic Level Input Pin (Internal Pullup)
        3. 7.3.9.3 Open Drain Pin
        4. 7.3.9.4 Push Pull Pin
        5. 7.3.9.5 Four Level Input Pin
      10. 7.3.10 Current Sense Amplifiers
        1. 7.3.10.1 Current Sense Amplifier Operation
      11. 7.3.11 Active Demagnetization
        1. 7.3.11.1 Automatic Synchronous Rectification Mode (ASR Mode)
          1. 7.3.11.1.1 Automatic Synchronous Rectification in Commutation
          2. 7.3.11.1.2 Automatic Synchronous Rectification in PWM Mode
        2. 7.3.11.2 Automatic Asynchronous Rectification Mode (AAR Mode)
      12. 7.3.12 Cycle-by-Cycle Current Limit
        1. 7.3.12.1 Cycle by Cycle Current Limit with 100% Duty Cycle Input
      13. 7.3.13 Protections
        1. 7.3.13.1 VM Supply Undervoltage Lockout (RESET)
        2. 7.3.13.2 AVDD Undervoltage Protection (AVDD_UV)
        3. 7.3.13.3 GVDD Undervoltage Lockout (GVDD_UV)
        4. 7.3.13.4 VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 7.3.13.5 Overvoltage Protections (OV)
        6. 7.3.13.6 Overcurrent Protection (OCP)
          1. 7.3.13.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.13.6.2 OCP Automatic Retry (OCP_MODE = 01b)
          3. 7.3.13.6.3 OCP Report Only (OCP_MODE = 10b)
          4. 7.3.13.6.4 OCP Disabled (OCP_MODE = 11b)
        7. 7.3.13.7 Thermal Warning (OTW)
        8. 7.3.13.8 Thermal Shutdown (OTS)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Operating Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT or nSLEEP Reset Pulse)
      2. 7.4.2 DRVOFF Functionality
    5. 7.5 SPI Communication
      1. 7.5.1 Programming
        1. 7.5.1.1 SPI Format
  9. 8 Register Map
    1. 8.1 STATUS Registers
    2. 8.2 CONTROL Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Three-Phase Brushless-DC Motor Control
        1. 9.2.1.1 Detailed Design Procedure
          1. 9.2.1.1.1 Motor Voltage
          2. 9.2.1.1.2 Using Active Demagnetization
          3. 9.2.1.1.3 Current Limit Implementation
          4. 9.2.1.1.4 Current Sensing and Output Filtering
          5. 9.2.1.1.5 Power Dissipation and Junction Temperature Losses
        2. 9.2.1.2 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Bulk Capacitance
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
      3. 9.4.3 Thermal Considerations
        1. 9.4.3.1 Power Dissipation
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

TJ = –40°C to +150°C, VVM = 4.5 to 65 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES
IVMQ VM sleep mode current VVM > 6V, nSLEEP = 0, TA = 25°C 1.5 3 µA
nSLEEP = 0 2.5 8 µA
IVMS VM standby mode current
 		 VVM > 6V, nSLEEP = 1, INHx = INLx = 0, SPI = 'OFF', TA = 25°C 6.6 8.2 mA
nSLEEP = 1, INHx = INLx = 0, SPI = 'OFF' 6.6 8.2 mA
IVMS VM standby mode current
 		 VVM > 6V, nSLEEP = 1, INHx = INLx = 0, SPI = 'OFF', TA = 25°C, ASR and AAR disabled 6.1 7.5 mA
IVMS VM standby mode current
 		 nSLEEP = 1, INHx = INLx = 0, SPI = 'OFF', ASR and AAR disabled 6.1 7.5 mA
IVM VM operating mode current
 		 VVM > 6V, nSLEEP = 1, fPWM = 20kHz 7.6 9.8 mA
 nSLEEP =1, fPWM = 20kHz 7.6 9.8 mA
nSLEEP =1, fPWM =100kHz 10.1 13.4 mA
VGVDD Analog regulator voltage 0mA ≤ IGVDD ≤ 30mA; (External Load); VM > 6V 4.75 5 5.25 V
VGVDD Analog regulator voltage 0mA ≤ IGVDD ≤ 30mA; (External Load); VM = 4.5V 3.7 4.5 V
VAVDD Analog regulator voltage 0mA ≤ IAVDD ≤ 30mA; (External Load) 3.1 3.3 3.465 V
IGVDD External analog regulator load IAVDD = 0mA 30 mA
IAVDD External analog regulator load IGVDD = 0mA 30 mA
VVCP Charge pump regulator voltage VCP with respect to VM, (VVM > 6V) 4 5 6 V
tWAKE Wakeup time VVM > VUVLO, nSLEEP = 1 to outputs ready and nFAULT released 5.5 ms
tSLEEP Sleep Pulse time nSLEEP = 0 period to enter sleep mode 120 µs
tRST Reset Pulse time nSLEEP = 0 period to reset faults 20 40 µs
LOGIC-LEVEL INPUTS (DRVOFF, INHx, INLx, nSLEEP, SCLK, SDI, OCP)
VIL Input logic low voltage 0 0.6 V
VIH Input logic high voltage nSLEEP 1.6 5.5 V
Other Pins 1.5 5.5 V
VHYS Input logic hysteresis nSLEEP 95 300 425 mV
Other PIns 180 300 425 mV
IIL Input logic low current VPIN (Pin Voltage) = 0V –1 1 µA
IIH Input logic high current nSLEEP, VPIN (Pin Voltage) = 5V 15 35 µA
IIH Input logic high current Other pins, VPIN (Pin Voltage) = 5V 30 75 µA
RPD Input pulldown resistance nSLEEP 150 200 300 kΩ
Other pins 70 100 130 kΩ
tGED Deglitch time DRVOFF pin 0.6 1.15 1.7 µs
CID Input capacitance 30 pF
LOGIC-LEVEL INPUTS (nSCS)
VIL Input logic low voltage 0 0.6 V
VIH Input logic high voltage 1.5 5.5 V
VHYS Input logic hysteresis 300 mV
IIL Input logic low current VPIN (Pin Voltage) = 0V 75 µA
IIH Input logic high current VPIN (Pin Voltage) = 5V –1 25 µA
RPU Input pullup resistance 80 100 130 kΩ
CID Input capacitance 30 pF
FOUR-LEVEL INPUTS (GAIN, MODE_SR, SLEW)
VL1 Input mode 1 voltage Tied to AGND 0 0.2*GVDD V
VL2 Input mode 2 voltage Hi-Z 0.27*GVDD 0.5*GVDD 0.55*GVDD V
VL3 Input mode 3 voltage 47kΩ +/- 5% tied to GVDD 0.6*GVDD 0.76*GVDD 0.9*GVDD V
VL4 Input mode 4 voltage Tied to GVDD 0.94*GVDD GVDD V
RPU Input pullup resistance To GVDD 80 100 120 kΩ
RPD Input pulldown resistance To AGND 80 100 120 kΩ
OPEN-DRAIN OUTPUTS (nFAULT)
VOL Output logic low voltage IOD = 5mA 0.4 V
IOH Output logic high current VOD = 5V –1 1 µA
COD Output capacitance 30 pF
PUSH-PULL OUTPUTS (SDO)
VOL Output logic low voltage IOP = 5mA 0 0.4 V
VOH Output logic high voltage IOP = 5mA, SDO_VSEL = 0 2.5 AVDD V
VOH Output logic high voltage IOP = 5mA, SDO_VSEL = 1, VVM > 6V 4 GVDD V
IOL Output logic low leakage current VOP = 0V –1 1 µA
IOH Output logic high leakage current VOP = 5V –1 1 µA
COD Output capacitance 30 pF
DRIVER OUTPUTS
RDS(ON) Total MOSFET on resistance (High-side + Low-side) VVM > 6V, IOUT = 1A, TA = 25°C 400 505 mΩ
VVM < 6V, IOUT = 1A, TA = 25°C 407 515 mΩ
VVM > 6V, IOUT = 1A, TJ = 150°C 690 790 mΩ
VVM < 6V, IOUT = 1A, TJ = 150°C 705 810 mΩ
SR Phase pin slew rate switching low to high (Rising from 20 % to 80 %)
 		 VVM = 24V, SLEW = 00b or SLEW pin tied to AGND, IOUTx = 1A 630 1100 1760 V/us
VVM = 24V, SLEW = 01b or SLEW pin to Hi-Z, IOUTx = 1A 260 500 900 V/us
VVM = 24V, SLEW = 10b or SLEW pin to 47kΩ +/- 5% to GVDD, IOUTx = 1A 135 250 455 V/us
VVM = 24V, SLEW = 11b or SLEW pin tied to GVDD, IOUTx = 1A 22 60 90 V/us
SR Phase pin slew rate switching high to low (Falling from 80 % to 20 %
 		 VVM = 24V, SLEW = 00b or SLEW pin tied to AGND, IOUTx = 1A 500 1100 1760 V/us
VVM = 24V, SLEW = 01b or SLEW pin to Hi-Z, IOUTx = 1A 240 500 845 V/us
VVM = 24V, SLEW = 10b or SLEW pin to 47kΩ +/- 5% to GVDD, IOUTx = 1A 120 250 490 V/us
VVM = 24V, SLEW = 11b or SLEW pin tied to GVDD, IOUTx = 1A 30 50 85 V/us
ILEAK Leakage current on OUTx VOUTx = VVM, nSLEEP = 1 2 mA
Leakage current on OUTx  VOUTx = 0 V, nSLEEP = 1 1 µA
tDEAD Output dead time (high to low / low to high) VVM = 24V, SLEW = 00b or SLEW pin tied to AGND, HS driver ON to LS driver OFF 65 150 ns
VVM = 24V, SLEW = 01b or SLEW pin to Hi-Z, HS driver ON to LS driver OFF 100 250 ns
VVM = 24V, SLEW = 10b or SLEW pin to 47kΩ +/- 5% to GVDD, HS driver ON to LS driver OFF 100 250 ns
VVM = 24V, SLEW = 11b or SLEW pin tied to GVDD, HS driver ON to LS driver OFF 250 550 ns
tPD Propagation delay (high-side / low-side ON/OFF) VVM = 24V, INHx = 1 to OUTx transisition, SLEW = 00b or SLEW pin tied to AGND 35 85 ns
VVM = 24V, INHx = 1 to OUTx transisition, SLEW = 01b or SLEW pin to Hi-Z 40 100 ns
VVM = 24V, INHx = 1 to OUTx transisition, SLEW = 10b or SLEW pin to 47kΩ +/- 5% to GVDD 45 140 ns
VVM = 24 V, INHx = 1 to OUTx transisition, SLEW = 11b or SLEW pin tied to GVDD 1200 1900 ns
tMIN_PULSE Minimum output pulse width
SLEW = 00b or SLEW pin tied to AGND
 		 110 ns
CURRENT SENSE AMPLIFIER
GCSA Current sense gain (SPI Device) CSA_GAIN = 00 0.4 V/A
GCSA Current sense gain (SPI Device) CSA_GAIN = 01 1 V/A
GCSA Current sense gain (SPI Device) CSA_GAIN = 02 2.5 V/A
GCSA Current sense gain (SPI Device) CSA_GAIN = 03 5 V/A
GCSA Current sense gain (HW Device) GAIN pin tied to AGND 0.4 V/A
GCSA Current sense gain (HW Device) GAIN pin to Hi-Z 1 V/A
GCSA Current sense gain (HW Device) GAIN pin to 47kΩ ± 5% to GVDD 2.5 V/A
GCSA Current sense gain (HW Device) GAIN pin tied to GVDD 5 V/A
GCSA_ERR Current sense gain error TJ = 25°C, 0A ≤ LS FET Current ≤ 2.5A (Current direction from OUTx to PGND) -4 4 %
TJ = 25°C, 2.5A ≤ LS FET Current ≤ 3.5A (Current direction from OUTx to PGND) -5 5 %
0A ≤ LS FET Current ≤ 2.5A (Current direction from OUTx to PGND) –5 5 %
2.5A ≤ LS FET Current ≤ 3.5A ; (Current direction from OUTx to PGND) -5 8.7 %
GCSA_ERR Current sense gain error TJ = 25°C, 0A ≤ LS FET Current ≤ 2A (Current direction from PGND to OUTx) -4 4 %
GCSA_ERR Current sense gain error 0A ≤ LS FET Current ≤ 2A (Current direction from PGND to OUTx) -6 6 %
IMATCH Current sense gain error matching between phases A, B and C TA = 25°C -5 5 %
-5 5 %
FSPOS Full scale positive current measurement Current direction from PGND to OUTx in the LS FET, VREF = 3.3V 2 A
FSNEG Full scale negative current measurement Current direction from OUTx to PGND in the LS FET, VREF = 3.3V –3.5 A
VLINEAR SOX output voltage linear range 0.25 VREF-0.25 V
IOFFSET Current sense offset TJ = 25°C, Phase current = 0A, VREF ≤ 3.6V –20 -10 5 mA
IOFFSET Current sense offset TJ = 25°C, Phase current = 0A, 3.6V ≤ VREF ≤ 5.5V –20 -10 10 mA
tSET Settling time to ±1%, 30 pF Step on SOX = 1.2V 1.2 μs
tCSA_ON_DELAY Delay from INLx turn on to current sense amplifier turn on  SR = 1000V/μs or 500V/μs or 250V/μs 500 700 ns
tCSA_ON_DELAY Delay from INLx turn on to current sense amplifier turn on SR = 50V/μs 4300 5000 ns
IDRIFT Drift offset Phase current = 0A –60 60 µA/C
IVREF VREF input current VREF = 3.0V, nSLEEP = 0 or 1 15 µA
PULSE-BY-PULSE CURRENT LIMIT
VLIM Voltage on ILIMIT pin for cycle by cycle current limit VREF/2 VREF - 0.25 V
VLIM_DIS Voltage on ILIMIT pin for disabling cycle by cycle current limit VREF GVDD V
ILIMIT Current limit corresponding to VLIM pin voltage range 0 4 A
ILIM_AC Current limit accuracy VREF = 3.3V, ILIMIT > 1A –6 6 %
ILIM_AC Current limit accuracy VREF = 3.3V, 0.5 A < ILIMIT < 1A –10 10 %
tBLANK Cycle by cycle current limit blank time SLEW = 00b or 01b or 10b, ILIM_BLANK_SEL = 00b, HW variant 1.75 µs
tBLANK Cycle by cycle current limit blank time SLEW = 00b or 01b or 10b, ILIM_BLANK_SEL = 01b 2.25 µs
tBLANK Cycle by cycle current limit blank time SLEW = 00b or 01b or 10b, ILIM_BLANK_SEL = 10b 2.75 µs
tBLANK Cycle by cycle current limit blank time SLEW = 00b or 01b or 10b, ILIM_BLANK_SEL = 11b 3.75 µs
tBLANK Cycle by cycle current limit blank time SLEW = 11b, ILIM_BLANK_SEL = 00b, HW variant 5.5 µs
tBLANK Cycle by cycle current limit blank time SLEW = 11b, ILIM_BLANK_SEL = 01b 6 µs
tBLANK Cycle by cycle current limit blank time SLEW = 11b, ILIM_BLANK_SEL = 10b 6.5 µs
tBLANK Cycle by cycle current limit blank time SLEW = 11b, ILIM_BLANK_SEL = 11b 7.5 µs
PROTECTION CIRCUITS
VUVLO Supply undervoltage lockout (UVLO) VM rising 4.2 4.35 4.5 V
VM falling 4.0 4.15 4.3 V
VUVLO_HYS Supply undervoltage lockout hysteresis Rising to falling threshold 65 200 415 mV
tUVLO Supply undervoltage deglitch time 3 6 10 µs
VOVP Supply overvoltage protection (OVP)
(SPI Device)		 Supply rising, OVP_EN = 1, OVP_SEL = 0 60 62.5 65 V
Supply falling, OVP_EN = 1, OVP_SEL = 0 58 61 63.5 V
Supply rising, OVP_EN = 1, OVP_SEL = 1 32.5 34 35 V
Supply falling, OVP_EN = 1, OVP_SEL = 1 32 33 34 V
VOVP_HYS Supply overvoltage protection (OVP)
(SPI Device)		 Rising to falling threshold, OVP_SEL = 1 0.74 0.8 0.85 V
Rising to falling threshold, OVP_SEL = 0 1.35 1.45 1.55 V
tOVP Supply overvoltage deglitch time 2.5 6.5 12 µs
VCPUV Charge pump undervoltage lockout (above VM) Supply rising 2.1 2.7 3.2 V
Supply falling 1.8 2.45 2.95 V
VCPUV_HYS Charge pump UVLO hysteresis Rising to falling threshold 105 150 200 mV
VAVDD_UV Analog regulator undervoltage lockout Supply rising 2.7 2.85 3 V
Supply falling 2.5 2.65 2.8 V
VAVDD_UV_HYS Analog regulator undervoltage lockout hysteresis Rising to falling threshold 180 200 240 mV
VGVDD_UV GVDD regulator undervoltage lockout Supply rising 3.1 3.3 3.5 V
VGVDD_UV GVDD regulator undervoltage lockout Supply falling 2.9 3.1 3.3 V
VGVDD_UV_HYS Analog regulator undervoltage lockout hysteresis Rising to falling threshold 145 190 265 mV
IOCP Overcurrent protection trip point (SPI Device) OCP_LVL = 00b or 01b 4.5 9 A
IOCP Overcurrent protection trip point (SPI Device) OCP_LVL = 10b or 11b 2.5 5 A
IOCP Overcurrent protection trip point (HW Device) OCP pin tied to AGND or OCP pin HiZ 4.5 9 A
IOCP Overcurrent protection trip point (HW Device) OCP tied to GVDD 2.5 5 A
tOCP Overcurrent protection deglitch time
(SPI Device)		 OCP_DEG = 00b 0.2 0.6 1.2 µs
OCP_DEG = 01b 0.6 1.25 1.8 µs
OCP_DEG = 10b 1 1.6 2.5 µs
OCP_DEG = 11b 1.4 2 3 µs
Overcurrent protection deglitch time
(HW Device)		 0.6 1.25 2 µs
tRETRY Overcurrent protection retry time
(SPI Device)		 OCP_RETRY = 0 4 5 6 ms
OCP_RETRY = 1 425 500 575 ms
tRETRY Overcurrent protection retry time
(HW Device)		 4 5 6 ms
TOTW Thermal warning temperature Die temperature (TJ) 160 170 180 °C
TOTW_HYS Thermal warning hysteresis Die temperature (TJ) 25 30 35 °C
TTSD Thermal shutdown temperature  Die temperature (TJ) 175 185 195 °C
TTSD_HYS Thermal shutdown hysteresis  Die temperature (TJ) 25 30 35 °C