SLOSE54C June   2020  – July 2022 DRV8428

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Indexer Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Stepper Motor Driver Current Ratings
        1. 7.3.1.1 Peak Current Rating
        2. 7.3.1.2 RMS Current Rating
        3. 7.3.1.3 Full-Scale Current Rating
      2. 7.3.2 PWM Motor Drivers
      3. 7.3.3 Microstepping Indexer
      4. 7.3.4 Controlling VREF with an MCU DAC
      5. 7.3.5 Current Regulation, Off-time and Decay Modes
        1. 7.3.5.1 Mixed Decay
        2. 7.3.5.2 Smart tune Dynamic Decay
        3. 7.3.5.3 Smart tune Ripple Control
        4. 7.3.5.4 Blanking time
      6. 7.3.6 Linear Voltage Regulators
      7. 7.3.7 Logic Level, tri-level, quad-level and seven-level Pin Diagrams
        1. 7.3.7.1 EN/nFAULT Pin
      8. 7.3.8 Protection Circuits
        1. 7.3.8.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.8.2 Overcurrent Protection (OCP)
        3. 7.3.8.3 Thermal Shutdown (OTSD)
        4. 7.3.8.4 Fault Condition Summary
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode (nSLEEP = 0)
      2. 7.4.2 Disable Mode (nSLEEP = 1, EN/nFAULT = 0/Hi-Z)
      3. 7.4.3 Operating Mode (nSLEEP = 1, EN/nFAULT = 1)
      4. 7.4.4 Functional Modes Summary
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stepper Motor Speed
        2. 8.2.2.2 Current Regulation
        3. 8.2.2.3 Decay Modes
        4. 8.2.2.4 Application Curves
      3. 8.2.3 Thermal Application
        1. 8.2.3.1 Power Dissipation
          1. 8.2.3.1.1 Conduction Loss
          2. 8.2.3.1.2 Switching Loss
          3. 8.2.3.1.3 Power Dissipation Due to Quiescent Current
          4. 8.2.3.1.4 Total Power Dissipation
        2. 8.2.3.2 Device Junction Temperature Estimation
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.7.1 EN/nFAULT Pin

The EN/nFAULT pin is used to enable the driver and also used for fault reporting. Figure 7-15 shows the internal circuitry connected to the EN/nFAULT pin. When the pin is intended to be used for both enabling the driver and fault reporting, the external R-C has to be connected. When the pin is only intended for enabling and disabling the driver, the R-C is not required.

To enable the H-bridges, the pin must be driven high. Floating the pin or connecting the pin to ground forces the bridge to become high-Z.

When a fault is detected, EN/nFAULT pin is forced low by turning on Q1 - which discharges the capacitor C1. The H-bridges are disabled when the voltage on the EN/nFAULT pin falls below the VIL threshold. The bridges stay disabled till the fault condition is removed or a second MCU pin directly applies a voltage higher than VIH to the EN/nFAULT pin. Thereafter, Q1 is turned off and C1 charges back through the resistor R1.

The typical delay from EN/nFAULT rising edge to the enabling the H-bridges is 100 µs. The time constant of R1 * C1 must be less than 20 µs. Typical values of the resistors R2 and R3 are 16 kΩ and 2 MΩ respectively. When the EN/nFAULT pin is permanently tied high, a fault will cause additional leakage current due to Q1 being ON.

GUID-BA3EE815-E961-4105-987B-8CD95B0A8311-low.gifFigure 7-15 EN/nFAULT Pin