SLOSE79B August   2022  – October 2023 DRV8462

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
      1. 6.5.1 SPI Timing Requirements
      2. 6.5.2 STEP and DIR Timing Requirements
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Interface of Operation
      2. 7.3.2  Stepper Motor Driver Current Ratings
        1. 7.3.2.1 Peak Current Rating
        2. 7.3.2.2 RMS Current Rating
        3. 7.3.2.3 Full-Scale Current Rating
      3. 7.3.3  PWM Motor Drivers
      4. 7.3.4  Microstepping Indexer
      5. 7.3.5  Indexer Output
        1. 7.3.5.1 nHOME Output
      6. 7.3.6  Automatic Microstepping Mode
      7. 7.3.7  Custom Microstepping Table
      8. 7.3.8  Current Regulation
      9. 7.3.9  Internal Reference Voltage
      10. 7.3.10 Standstill Power Saving Mode
      11. 7.3.11 Current Regulation Decay Modes
        1. 7.3.11.1 Slow Decay
        2. 7.3.11.2 Mixed Decay
        3. 7.3.11.3 Smart tune Dynamic Decay
        4. 7.3.11.4 Smart tune Ripple Control
        5. 7.3.11.5 PWM OFF Time
        6. 7.3.11.6 Current Regulation Blanking Time and Deglitch Time
      12. 7.3.12 Current Sensing with External Resistor
      13. 7.3.13 Silent step decay mode
      14. 7.3.14 Auto-torque Dynamic Current Adjustment
        1. 7.3.14.1 Auto-torque Learning Routine
        2. 7.3.14.2 Current Control Loop
        3. 7.3.14.3 PD Control Loop
        4. 7.3.14.4 Efficiency Improvement with Auto-torque
      15. 7.3.15 Charge Pump
      16. 7.3.16 Linear Voltage Regulator
      17. 7.3.17 VCC Voltage Supply
      18. 7.3.18 Logic Level, Tri-Level and Quad-Level Pin Diagrams
      19. 7.3.19 Spread spectrum
      20. 7.3.20 Protection Circuits
        1. 7.3.20.1  VM Undervoltage Lockout
        2. 7.3.20.2  VCP Undervoltage Lockout (CPUV)
        3. 7.3.20.3  Logic Supply Power on Reset (POR)
        4. 7.3.20.4  Overcurrent Protection (OCP)
          1. 7.3.20.4.1 Latched Shutdown
          2. 7.3.20.4.2 Automatic Retry
        5. 7.3.20.5  Stall Detection
        6. 7.3.20.6  Open-Load Detection (OL)
        7. 7.3.20.7  Overtemperature Warning (OTW)
        8. 7.3.20.8  Thermal Shutdown (OTSD)
          1. 7.3.20.8.1 Latched Shutdown
          2. 7.3.20.8.2 Automatic Retry
        9. 7.3.20.9  Supply voltage sensing
        10. 7.3.20.10 nFAULT Output
        11. 7.3.20.11 Fault Condition Summary
      21. 7.3.21 Device Functional Modes
        1. 7.3.21.1 Sleep Mode
        2. 7.3.21.2 Disable Mode
        3. 7.3.21.3 Operating Mode
        4. 7.3.21.4 nSLEEP Reset Pulse
        5. 7.3.21.5 Functional Modes Summary
    4. 7.4 Programming
      1. 7.4.1 Serial Peripheral Interface (SPI) Communication
        1. 7.4.1.1 SPI Format
        2. 7.4.1.2 SPI for Multiple Target Devices in Daisy Chain Configuration
        3. 7.4.1.3 SPI for Multiple Target Devices in Parallel Configuration
    5. 7.5 Register Maps
      1. 7.5.1 Status Registers
        1. 7.5.1.1 FAULT (address = 0x00) [Default = 00h]
        2. 7.5.1.2 DIAG1 (address = 0x01) [Default = 00h]
        3. 7.5.1.3 DIAG2 (address = 0x02) [Default = 00h]
        4. 7.5.1.4 DIAG3 (address = 0x03) [Default = 00h]
      2. 7.5.2 Control Registers
        1. 7.5.2.1  CTRL1 (address = 0x04) [Default = 0Fh]
        2. 7.5.2.2  CTRL2 (address = 0x05) [Default = 06h]
        3. 7.5.2.3  CTRL3 (address = 0x06) [Default = 38h]
        4. 7.5.2.4  CTRL4 (address = 0x07) [Default = 49h]
        5. 7.5.2.5  CTRL5 (address = 0x08) [Default = 03h]
        6. 7.5.2.6  CTRL6 (address = 0x09) [Default = 20h]
        7. 7.5.2.7  CTRL7 (address = 0x0A) [Default = FFh]
        8. 7.5.2.8  CTRL8 (address = 0x0B) [Default = 0Fh]
        9. 7.5.2.9  CTRL9 (address = 0x0C) [Default = 10h]
        10. 7.5.2.10 CTRL10 (address = 0x0D) [Default = 80h]
        11. 7.5.2.11 CTRL11 (address = 0x0E) [Default = FFh]
        12. 7.5.2.12 CTRL12 (address = 0x0F) [Default = 20h]
        13. 7.5.2.13 CTRL13 (address = 0x10) [Default = 10h]
        14. 7.5.2.14 CTRL14 (address = 0x3C) [Default = 58h]
      3. 7.5.3 Indexer Registers
        1. 7.5.3.1 INDEX1 (address = 0x11) [Default = 80h]
        2. 7.5.3.2 INDEX2 (address = 0x12) [Default = 80h]
        3. 7.5.3.3 INDEX3 (address = 0x13) [Default = 80h]
        4. 7.5.3.4 INDEX4 (address = 0x14) [Default = 82h]
        5. 7.5.3.5 INDEX5 (address = 0x15) [Default = B5h]
      4. 7.5.4 Custom Microstepping Registers
        1. 7.5.4.1 CUSTOM_CTRL1 (address = 0x16) [Default = 00h]
        2. 7.5.4.2 CUSTOM_CTRL2 (address = 0x17) [Default = 00h]
        3. 7.5.4.3 CUSTOM_CTRL3 (address = 0x18) [Default = 00h]
        4. 7.5.4.4 CUSTOM_CTRL4 (address = 0x19) [Default = 00h]
        5. 7.5.4.5 CUSTOM_CTRL5 (address = 0x1A) [Default = 00h]
        6. 7.5.4.6 CUSTOM_CTRL6 (address = 0x1B) [Default = 00h]
        7. 7.5.4.7 CUSTOM_CTRL7 (address = 0x1C) [Default = 00h]
        8. 7.5.4.8 CUSTOM_CTRL8 (address = 0x1D) [Default = 00h]
        9. 7.5.4.9 CUSTOM_CTRL9 (address = 0x1E) [Default = 00h]
      5. 7.5.5 Auto torque Registers
        1. 7.5.5.1  ATQ_CTRL1 (address = 0x1F) [Default = 00h]
        2. 7.5.5.2  ATQ_CTRL2 (address = 0x20) [Default = 00h]
        3. 7.5.5.3  ATQ_CTRL3 (address = 0x21) [Default = 00h]
        4. 7.5.5.4  ATQ_CTRL4 (address = 0x22) [Default = 20h]
        5. 7.5.5.5  ATQ_CTRL5 (address = 0x23) [Default = 00h]
        6. 7.5.5.6  ATQ_CTRL6 (address = 0x24) [Default = 00h]
        7. 7.5.5.7  ATQ_CTRL7 (address = 0x25) [Default = 00h]
        8. 7.5.5.8  ATQ_CTRL8 (address = 0x26) [Default = 00h]
        9. 7.5.5.9  ATQ_CTRL9 (address = 0x27) [Default = 00h]
        10. 7.5.5.10 ATQ_CTRL10 (address = 0x28) [Default = 08h]
        11. 7.5.5.11 ATQ_CTRL11 (address = 0x29) [Default = 0Ah]
        12. 7.5.5.12 ATQ_CTRL12 (address = 0x2A) [Default = FFh]
        13. 7.5.5.13 ATQ_CTRL13 (address = 0x2B) [Default = 05h]
        14. 7.5.5.14 ATQ_CTRL14 (address = 0x2C) [Default = 0Fh]
        15. 7.5.5.15 ATQ_CTRL15 (address = 0x2D) [Default = 00h]
        16. 7.5.5.16 ATQ_CTRL16 (address = 0x2E) [Default = FFh]
        17. 7.5.5.17 ATQ_CTRL17 (address = 0x2F) [Default = 00h]
        18. 7.5.5.18 ATQ_CTRL18 (address = 0x30) [Default = 00h]
      6. 7.5.6 Silent Step Registers
        1. 7.5.6.1 SS_CTRL1 (address = 0x31) [Default = 00h]
        2. 7.5.6.2 SS_CTRL2 (address = 0x32) [Default = 00h]
        3. 7.5.6.3 SS_CTRL3 (address = 0x33) [Default = 00h]
        4. 7.5.6.4 SS_CTRL4 (address = 0x34) [Default = 00h]
        5. 7.5.6.5 SS_CTRL5 (address = 0x35) [Default = FFh]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stepper Motor Speed
      3. 8.2.3 Application Performance Plots
      4. 8.2.4 Thermal Application
        1. 8.2.4.1 Power Dissipation
        2. 8.2.4.2 Conduction Loss
        3. 8.2.4.3 Switching Loss
        4. 8.2.4.4 Power Dissipation Due to Quiescent Current
        5. 8.2.4.5 Total Power Dissipation
        6. 8.2.4.6 Device Junction Temperature Estimation
        7. 8.2.4.7 Thermal Images
  10. 9 Thermal Considerations
    1. 9.1 DDV Package
    2. 9.2 DDW Package
    3. 9.3 PCB Material Recommendation
  11. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance
    2. 10.2 Power Supplies
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Typical values are at TA = 25°C and VVM = 24 V. All limits are over recommended operating conditions, unless otherwise noted.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
POWER SUPPLIES (VM, DVDD)
IVMVM operating supply currentENABLE = 1, nSLEEP = 1, No motor load, VCC = External 5V

5

8

mA
ENABLE = 1, nSLEEP = 1, No motor load, VCC = DVDD

8.5

11

IVMQVM sleep mode supply currentnSLEEP = 03

8

μA
tSLEEPSleep timenSLEEP = 0 to sleep-mode120μs
tRESETnSLEEP reset pulsenSLEEP low to clear fault2040μs
tWAKEWake-up timeH/W interface, nSLEEP = 1 to output transition0.851.2ms

SPI interface, nSLEEP = 1 to SPI ready

0.16

0.25

ms
tONTurn-on time1VM > UVLO to output transition11.3ms
VDVDDInternal regulator voltageNo external load, 6 V < VVM < 65 V4.7555.25V
No external load, VVM = 4.5 V

4.35

4.45

V

CHARGE PUMP (VCP, CPH, CPL)
VVCP

VCP operating voltage

6 V < VVM < 65 VVVM

+ 5

V

f

VCP

Charge pump switching frequency

VVM > UVLO; nSLEEP = 1

357

kHz

fCLK

Internal digital clock frequency

VVM > UVLO; nSLEEP = 1

10

MHz

LOGIC-LEVEL INPUTS (STEP, DIR, MODE, DECAY1, nSCS, SCLK, SDI, nSLEEP)
VILInput logic-low voltage00.6V
VIHInput logic-high voltage (all pins except DECAY1)1.55.5V
VIH_DECAY1Input logic-high voltage (DECAY1 pin)

2.7

5.5

V

VHYSInput logic hysteresis (all pins except nSLEEP)100mV
VHYS_SLEEP

nSLEEP logic hysteresis

300

mV

IILInput logic-low current (all pins except nSCS)VIN = 0 V–11μA

IIL_nSCS

nSCS logic-low current

nSCS = 0V

8

12

μA
IIHInput logic-high current (all pins except nSCS, 200k internal pull-down resistance)VIN = DVDD50μA
IIH_nSCSnSCS logic-high currentnSCS = DVDD

0.1

μA

TRI-LEVEL INPUTS (M0, DECAY0, ENABLE)
VI1_triInput logic-low voltageTied to GND00.6V
VI2_triInput Hi-Z voltage

Hi-Z

1.8

2

2.2

V
VI3_triInput logic-high voltageTied to DVDD

2.7

5.5

V
IO_triOutput pull-up current

10.5

μA
QUAD-LEVEL INPUTS (M1, TOFF)
VI1_quadInput logic-low voltageTied to GND

0

0.6

V

VI2_quad

Input second level voltage

330kΩ ± 5% to GND

1

1.25

1.4

V

VI3_quadInput Hi-Z voltageHi-Z

1.8

2

2.2

V

VI4_quadInput logic-high voltageTied to DVDD

2.7

5.5

V

IO_quadOutput pull-up current

10.5

μA

PUSH-PULL OUTPUT (SDO)

RPD,SDO

Internal pull-down resistance

5mA load, with respect to GND

30

60

Ω

RPU,SDO

Internal pull-up resistance

5mA load, with respect to VCC

60

110

Ω

ISDO

SDO Leakage Current1

VVM > 6 V, SDO = VCC and 0V

-2.5

2.5

μA
CONTROL OUTPUTS (nFAULT, nHOME)

VOL

Output logic-low voltage

IO = 5 mA

0.35

V

IOH

Output logic-high leakage

-1

1

μA
MOTOR DRIVER OUTPUTS (AOUT1, AOUT2, BOUT1, BOUT2)
RDS(ONH)High-side FET on resistanceTJ = 25 °C, IO = -5 A

50

60mΩ
TJ = 125 °C, IO = -5 A

75

94mΩ
TJ = 150 °C, IO = -5 A

85

107

mΩ
RDS(ONL)Low-side FET on resistanceTJ = 25 °C, IO = 5 A

46

55

mΩ
TJ = 125 °C, IO = 5 A

68

90mΩ
TJ = 150 °C, IO = 5 A

75

100

mΩ

ILEAK

Output leakage current to ground in Disable mode1

H-bridges are Hi-Z, VVM = 65 V

200

μA

tRFOutput rise/fall timeH/W interface, IO = 5 A, between 10% and 90%

140

ns
SPI interface, SR = 0b, IO = 5 A, between 10% and 90%

140

SPI interface, SR = 1b, IO = 5 A, between 10% and 90%

70

tD

Output dead time

VM = 24V, IO = 5 A

300

ns

PWM CURRENT CONTROL (VREF)

KV

Transimpedance gain

VREF = 3.3 V, DDW Package

0.625

0.66

0.695

V/A

VREF = 3.3 V, DDV Package

0.313

0.33

0.347

IVREF

VREF Pin Leakage Current

VREF = 3.3 V

50

nA
tOFFPWM off-timeTOFF = 0 or TOFF = 00b

9

μs
TOFF = 1 or TOFF = 01b19
TOFF = Hi-Z or TOFF = 10b

27

TOFF = 330kΩ to GND or TOFF = 11b

35

ΔITRIP_EXT

Current trip accuracy, external VREF input

10% to 20% full-scale current

-12

12

%

20% to 40% full-scale current

-8

5

40% to 100% full-scale current

-5

4

ΔITRIP_INTCurrent trip accuracy, internal VREF10% to 20% full-scale current

-12

12

%

20% to 40% full-scale current

-9

6

40% to 100% full-scale current

-6

5

IO,CH

AOUT and BOUT current matching

100% full-scale current

-2.5

2.5

%

tBLK

Current regulation blanking time

SPI interface, TBLANK_TIME = 00b

1

μs

H/W interface or SPI interface, TBLANK_TIME = 01b

1.5

SPI interface, TBLANK_TIME = 10b

2

SPI interface, TBLANK_TIME = 11b

2.5

tDEG

Current regulation deglitch time

0.5

μs
PROTECTION CIRCUITS
VMUVLOVM UVLO lockoutVM falling

4.1

4.23

4.35V
VM rising

4.2

4.354.46
VCCUVLO

VCC UVLO lockout

VCC connected to external voltage, VCC falling

2.7

2.8

2.9

V

VCC connected to external voltage, VCC rising

2.8

2.92

3.05

VUVLO,HYSUndervoltage hysteresisRising to falling threshold120mV

VRST

VM UVLO reset

VCC = DVDD, SPI interface, VM falling, device reset, no SPI communications

3.4

V

VCPUV

Charge pump undervoltage

VCP falling

VVM + 2

V

IOCPOvercurrent protectionCurrent through any FET, DDW Package

8

A
Current through any FET, DDV Package

16

A

tOCPOvercurrent detection delay

H/W Interface

2.2

μs

SPI Interface, TOCP = 0b

1.2

SPI Interface, TOCP = 1b

2.2

tRETRY

Overcurrent retry time

4.1

ms

tOL

Open load detection time

H/W Interface

60

ms

SPI Interface, OL_T = 00b

30

SPI Interface, OL_T = 01b

60

SPI Interface, OL_T = 10b

120

IOL

Open load current threshold

190

mA

TOTW

Overtemperature warning

SPI Interface, Die temperature TJ

135

150

165

°C

THYS_OTW

Overtemperature warning hysteresisSPI Interface, Die temperature TJ

20

°C
TOTSDThermal shutdownDie temperature TJ150165180°C
THYS_OTSDThermal shutdown hysteresisDie temperature TJ20°C
(1) Guaranteed by design