SNVSCT1A October   2025  – December 2025 LM5066H

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 PMBus Interface Timing Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Current Limit
      2. 7.3.2  Foldback Current Limit
      3. 7.3.3  Soft Start Disconnect (SFT_STRT)
      4. 7.3.4  Circuit Breaker
      5. 7.3.5  Power Limit
      6. 7.3.6  UVLO
      7. 7.3.7  OVLO
      8. 7.3.8  Power Good
      9. 7.3.9  VDD Sub-Regulator
      10. 7.3.10 Remote Temperature Sensing
      11. 7.3.11 Damaged MOSFET Detection
      12. 7.3.12 Analog Current Monitor (IMON)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Up Sequence
      2. 7.4.2 Gate Control
      3. 7.4.3 Fault Timer and Restart
      4. 7.4.4 Shutdown Control
      5. 7.4.5 Enabling/Disabling and Resetting
    5. 7.5 Programming
      1. 7.5.1 PMBus Command Support
      2. 7.5.2 Detailed Descriptions of PMBus Commands
        1. 7.5.2.1  OPERATION (01h, Read/Write Byte)
        2. 7.5.2.2  CLEAR_FAULTS (03h, Send Byte)
        3. 7.5.2.3  WRITE_PROTECT (10h, Read/Write Byte)
        4. 7.5.2.4  RESTORE_FACTORY_DEFAULTS (12h, Send Byte)
        5. 7.5.2.5  STORE_USER_ALL (15h, Send Byte)
        6. 7.5.2.6  RESTORE_USER_ALL (16h, Send Byte)
        7. 7.5.2.7  CAPABILITY (19h, Read Byte)
        8. 7.5.2.8  VOUT_UV_WARN_LIMIT (43h, Read/Write Word)
        9. 7.5.2.9  OT_FAULT_LIMIT (4Fh, Read/Write Word)
        10. 7.5.2.10 OT_WARN_LIMIT (51h, Read/Write Word)
        11. 7.5.2.11 VIN_OV_WARN_LIMIT (57h, Read/Write Word)
        12. 7.5.2.12 IIN_OC_WARN_LIMIT (5Dh, Read/Write Word)
        13. 7.5.2.13 STATUS_BYTE (78h, Read Byte)
        14. 7.5.2.14 STATUS_WORD (79h, Read Word)
        15. 7.5.2.15 STATUS_VOUT (7Ah, Read Byte)
        16. 7.5.2.16 STATUS_INPUT (7Ch, Read Byte)
        17. 7.5.2.17 STATUS_TEMPERATURE (7Dh, Read Byte)
        18. 7.5.2.18 STATUS_CML (7Eh, Read Byte)
        19. 7.5.2.19 STATUS_OTHER (7Fh, Read Byte)
        20. 7.5.2.20 STATUS_MFR_SPECIFIC (80h)
        21. 7.5.2.21 READ_EIN (86h, Block Read)
        22. 7.5.2.22 READ_VIN (88h, Read Word)
        23. 7.5.2.23 READ_IIN (89h, Read Word)
        24. 7.5.2.24 READ_VOUT (8Bh, Read Word)
        25. 7.5.2.25 READ_IOUT (8Ch, Read Word)
        26. 7.5.2.26 READ_TEMPERATURE_1 (8Dh, Read Word)
        27. 7.5.2.27 READ_POUT (96h, Read Word)
        28. 7.5.2.28 READ_PIN (97h, Read Word)
        29. 7.5.2.29 PMBUS_REVISION (98h, Read Byte)
        30. 7.5.2.30 MFR_ID (99h, Block Read)
        31. 7.5.2.31 MFR_MODEL (9Ah, Block Read)
        32. 7.5.2.32 MFR_REVISION (9Bh, Block Read)
        33. 7.5.2.33 USER_DATA (BCh, Read/Write Byte)
        34. 7.5.2.34 READ_VIN_MIN (A0h, Read Word)
        35. 7.5.2.35 READ_VIN_PEAK (A1h, Read Word)
        36. 7.5.2.36 READ_IIN_PEAK (A2h, Read Word)
        37. 7.5.2.37 READ_PIN_PEAK (A3h)
        38. 7.5.2.38 READ_VOUT_MIN (A4h, Read Word)
        39. 7.5.2.39 READ_TEMP_AVG (C7h, Read Word)
        40. 7.5.2.40 READ_TEMP_PEAK (C8h, Read Word)
        41. 7.5.2.41 READ_SAMPLE_BUF (C9h, Block Read)
        42. 7.5.2.42 POWER_CYCLE (CAh, Send Byte)
        43. 7.5.2.43 READ_VAUX (D0h, Read Word)
        44. 7.5.2.44 MFR_READ_IIN (D1h, Read Word)
        45. 7.5.2.45 MFR_READ_PIN (D2h)
        46. 7.5.2.46 MFR_IIN_OC_WARN_LIMIT (D3h, F8h, Read/Write Word)
        47. 7.5.2.47 MFR_PIN_OP_WARN_LIMIT (D4h, Read/Write Word)
        48. 7.5.2.48 CLEAR_PIN_PEAK (D6h, Send Byte)
        49. 7.5.2.49 GATE_MASK (D7h, Read/Write Byte)
        50. 7.5.2.50 ALERT_MASK (D8h, Read/Write Word)
        51. 7.5.2.51 READ_VAUX_AVG (D9h, Read Word)
        52. 7.5.2.52 BLOCK_READ (DAh, Block Read)
        53. 7.5.2.53 SAMPLES_FOR_AVG (DBh, Read/Write Byte)
        54. 7.5.2.54 READ_VIN_AVG (DCh, Read Word)
        55. 7.5.2.55 READ_VOUT_AVG (DDh, Read Word)
        56. 7.5.2.56 READ_IIN_AVG (DEh, Read Word)
        57. 7.5.2.57 READ_PIN_AVG (DFh, Read Word)
        58. 7.5.2.58 CLEAR_BB_RAM (E0h, Send Byte)
        59. 7.5.2.59 READ_DIAGNOSTIC_WORD (E1h, Read Word)
        60. 7.5.2.60 AVG_BLOCK_READ (E2h, Block Read)
        61. 7.5.2.61 BB_ERASE (E3h, Send Byte)
        62. 7.5.2.62 BB_CONFIG (E4h, Read/Write Byte)
        63. 7.5.2.63 OC_BLANKING_TIMERS (E5h, Read/Write Byte)
        64. 7.5.2.64 DELAY_CONFIG (E7h, Read/Write Byte)
        65. 7.5.2.65 WD_PLB_ TIMER (E8h, Read/Write Byte)
        66. 7.5.2.66 PK_MIN_AVG (E9h, Read/Write Byte)
        67. 7.5.2.67 P2t TIMER (EAh, Read/Write Byte)
        68. 7.5.2.68 FETCH_BB_EEPROM (EBh, Send Byte)
        69. 7.5.2.69 READ_BB_RAM (ECh, Block Read)
        70. 7.5.2.70 ADC_CONFIG_1 (EDh, Read/Write Byte)
        71. 7.5.2.71 ADC_CONFIG_2 (EEh, Read/Write Byte)
        72. 7.5.2.72 DEVICE_SETUP1 (CCh, Read/Write Byte)
        73. 7.5.2.73 DEVICE_SETUP2 (EFh, Read/Write Byte)
        74. 7.5.2.74 DEVICE_SETUP3 (F0h, Read/Write Byte)
        75. 7.5.2.75 DEVICE_SETUP4 (CDh, Read/Write Byte)
        76. 7.5.2.76 DEVICE_SETUP5 (CEh, Read/Write Byte)
        77. 7.5.2.77 IIN OFFSET CALIBRATION (F2h, Read/Write Byte)
        78. 7.5.2.78 STATUS_MFR_SPECIFIC_2 (F3h, Read Word)
        79. 7.5.2.79 READ_BB_EEPROM (F4h, Block Read)
        80. 7.5.2.80 BB_TIMER (F6h, Read Byte)
        81. 7.5.2.81 PMBUS_ADDR (F7h, Read/Write Byte)
      3. 7.5.3 Reading and Writing Telemetry Data and Warning Thresholds
      4. 7.5.4 Determining Telemetry Coefficients Empirically With Linear Fit
      5. 7.5.5 Writing Telemetry Data
      6. 7.5.6 PMBus Address Lines (ADR0, ADR1, ADR2)
      7. 7.5.7 SMBA Response
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 54V, 100A PMBus Hot Swap Design
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design-In Procedure
          1. 8.2.1.2.1 Selecting the Hotswap FETs
          2. 8.2.1.2.2 dv/dt based Start-Up
            1. 8.2.1.2.2.1 Choosing the VOUT Slew Rate
          3. 8.2.1.2.3 Select RSNS and CL Setting
          4. 8.2.1.2.4 Select Power Limit
          5. 8.2.1.2.5 Set Fault Timer
          6. 8.2.1.2.6 Check MOSFET SOA
          7. 8.2.1.2.7 Set UVLO and OVLO Thresholds
            1. 8.2.1.2.7.1 Option A
            2. 8.2.1.2.7.2 Option B
            3. 8.2.1.2.7.3 Option C
            4. 8.2.1.2.7.4 Option D
          8. 8.2.1.2.8 Power Good Pin
          9. 8.2.1.2.9 Input and Output Protection
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.8 Power Good

The LM5066Hx features a Power Good indicator pin (PGD) which requires an external pullup resistor to provide status indication to downstream circuits. The PGD pin's off-state voltage can operate above or below the VIN and OUT voltages.

The PGD signal asserts HIGH when all of the below conditions are met,

  • FB pin voltage exceeds the PGD threshold

  • Both GATE1-OUT and GATE2-OUT voltages indicate full enhancement (VGS1 >8V and VGS2 >8V)

  • Voltage across the FET (VDS) is less than 2V

The PGD signal pulls LOW when,

  • FB pin voltage drops below the PGD falling threshold

The output voltage threshold is typically set using a resistor divider network from output to the feedback pin. However, other voltages can be monitored as long as the FB pin voltage remains within its maximum rating. For threshold hysteresis, the device includes a 21μA current source at the FB pin. This current source remains disabled when FB voltage is below threshold. As output voltage increases and FB exceeds threshold, the current source activates, sourcing current from the pin to raise FB voltage. The PGD pin status can be read through the PMBus interface via either the STATUS_WORD (79h) or DIAGNOSTIC_WORD (E1h) registers.