SNVSCT1 October   2025 LM5066H

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Current Limit
      2. 7.3.2  Foldback Current Limit
      3. 7.3.3  Soft Start Disconnect (SFT_STRT)
      4. 7.3.4  Circuit Breaker
      5. 7.3.5  Power Limit
      6. 7.3.6  UVLO
      7. 7.3.7  OVLO
      8. 7.3.8  Power Good
      9. 7.3.9  VDD Sub-Regulator
      10. 7.3.10 Remote Temperature Sensing
      11. 7.3.11 Damaged MOSFET Detection
      12. 7.3.12 Analog Current Monitor (IMON)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Up Sequence
      2. 7.4.2 Gate Control
      3. 7.4.3 Fault Timer and Restart
      4. 7.4.4 Shutdown Control
      5. 7.4.5 Enabling/Disabling and Resetting
    5. 7.5 Programming
      1. 7.5.1 PMBus Command Support
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 54V, 100A PMBus Hot Swap Design
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design-In Procedure
          1. 8.2.1.2.1 Selecting the Hotswap FETs
          2. 8.2.1.2.2 dv/dt-Based Start-Up
            1. 8.2.1.2.2.1 Choosing the VOUT Slew Rate
          3. 8.2.1.2.3 Select RSNS and CL Setting
          4. 8.2.1.2.4 Select Power Limit
          5. 8.2.1.2.5 Set Fault Timer
          6. 8.2.1.2.6 Check MOSFET SOA
          7. 8.2.1.2.7 Set UVLO and OVLO Thresholds
            1. 8.2.1.2.7.1 Option A
            2. 8.2.1.2.7.2 Option B
            3. 8.2.1.2.7.3 Option C
            4. 8.2.1.2.7.4 Option D
          8. 8.2.1.2.8 Power Good Pin
          9. 8.2.1.2.9 Input and Output Protection
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Option Addendum
    2. 11.2 Tape and Reel Information
    3. 11.3 Mechanical Data

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|28
Thermal pad, mechanical data (Package|Pins)

5 Pin Configuration and Functions

LM5066H LM5066H1 PWP PackageTop ViewFigure 5-1 LM5066H1 PWP PackageTop View
LM5066H LM5066H2 QFN PackageTop View
Solder exposed pad to ground.
Figure 5-2 LM5066H2 QFN PackageTop View
Table 5-1 Pin Functions
PIN NAME

PIN NO.

DESCRIPTION

LM5066H1

LM5066H2

Exposed PadPad

Pad

Exposed pad of package
Solder to the ground plane to reduce thermal resistance
OUT1

13

Output feedback
Connect to the output rail (external MOSFET source). Internally used to determine the MOSFET VDS voltage for power limiting and to monitor the output voltage.
GATE12

14

Gate drive output
Connect to the external MOSFET's gate. Connect to single strong SOA MOSFET's gate for LM5066H2
SENSE3

16

Current sense input
The voltage across the current sense resistor (RSNS) is measured from VIN_K to this pin. If the voltage across RSNS reaches overcurrent threshold the load current is limited and the fault timer activates.
VIN_K4

17

Positive supply Kelvin pin
The input voltage is measured on this pin.
VIN5

18, 19, 20

Positive supply input
This pin is the input supply connection for the deviceA 10Ω resistor can be connected between VIN and input power supply. Connect a 100nF capacitor on this pin to ground for bypassing.
N/C6

-

No connection
UVLO/EN7

21

Undervoltage lockout
An external resistor divider from the system input voltage sets the undervoltage turn ON threshold.
OVLO8

22

Overvoltage lockout
An external resistor divider from the system input voltage sets the overvoltage turn off threshold.
AGND9

23

Circuit ground
Analog device ground. Connect to GND at the pin.
GND10

9, 15, 24, 35

Circuit ground
SDAI11

25

SMBus data input pin
Data input pin for SMBus. Connect to SDAO if the application does not require unidirectional isolation devices.
SDAO12

26

SMBus data output pin
Data output pin for SMBus. Connect to SDAI if the application does not require unidirectional isolation devices.
SCL13

27

SMBus clock
Clock pin for SMBus
SMBA14

28

SMBus alert line
Alert pin for SMBus, active low
VREF15

29

Internal reference
Internally generated precision reference used for analog to digital conversion. Connect a 1µF capacitor on this pin to ground for bypassing.
DIODE16

30

External diode
Connect this to a diode configured MMBT3904 NPN transistor for temperature monitoring.
VAUX17

31

Auxiliary voltage input
Auxiliary pin allows voltage telemetry from an external source. Full scale input of 2.97V.
ADR218

32

SMBUS address line 2
Tri-state address line. Should be connected to GND, VDD, or left floating.
ADR119

33

SMBUS address line 1
Tri-state address line. Should be connected to GND, VDD, or left floating.
ADR020

34

SMBUS address line 0
Tri-state address line. Should be connected to GND, VDD, or left floating.
VDD21

1

Internal sub-regulator output
Internally sub-regulated 4.85V bias supply. Connect a 1µF capacitor on this pin to ground for bypassing.
CL22

2

Current limit range
Connect this pin to GND or leave floating to set the nominal over current threshold at 50mV. Connecting CL to VDD sets the overcurrent threshold to be 25mV.
FB23

3

Power Good feedback
An external resistor divider from the output sets the output voltage at which the PGD pin switches.

SYNC

-

4

Synchronous turn ON and turn OFF of parallel controllers
Tie this pin of all parallel controllers for synchronous operation.

RETRY24

5

Fault retry input
This pin configures the power up fault retry behavior. When this pin is connected to GND or left floating, the device will continually try to engage power during a fault. If the pin is connected to VDD, the device will latch off during a fault.
TIMER25

6

Timing capacitor
An external capacitor connected to this pin sets insertion time delay, fault timeout period, and restart timing.
PWR26

7

Power limit set
An external resistor connected to this pin, in conjunction with the current sense resistor (RSNS), sets the maximum power dissipation allowed in the external series pass MOSFET.

IMON

27

8

Load current monitorAn external resistor needs to be connected from this pin to GND. IMON pin outputs current proportional to the load current.
PGD28

10

Power Good indicator
An open-drain output. This output is high when the voltage at the FB pin is above VFBTH and VGS1, VGS2 are high.

SFT_STRT

-

11

Soft start capacitor disconnectdvdt capacitor (Cdvdt) for inrush current limiting has to be connected from this pin to GND Internal switches connect Cdvdt to GATE1 during startup/retry. After successful startup, the Cdvdt cap is connected to OUT

GATE2

-

12

GATE2 drive outputConnect to the external Low RDS(ON) MOSFETs gate.