SNVSCT1 October   2025 LM5066H

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Current Limit
      2. 7.3.2  Foldback Current Limit
      3. 7.3.3  Soft Start Disconnect (SFT_STRT)
      4. 7.3.4  Circuit Breaker
      5. 7.3.5  Power Limit
      6. 7.3.6  UVLO
      7. 7.3.7  OVLO
      8. 7.3.8  Power Good
      9. 7.3.9  VDD Sub-Regulator
      10. 7.3.10 Remote Temperature Sensing
      11. 7.3.11 Damaged MOSFET Detection
      12. 7.3.12 Analog Current Monitor (IMON)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Up Sequence
      2. 7.4.2 Gate Control
      3. 7.4.3 Fault Timer and Restart
      4. 7.4.4 Shutdown Control
      5. 7.4.5 Enabling/Disabling and Resetting
    5. 7.5 Programming
      1. 7.5.1 PMBus Command Support
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 54V, 100A PMBus Hot Swap Design
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design-In Procedure
          1. 8.2.1.2.1 Selecting the Hotswap FETs
          2. 8.2.1.2.2 dv/dt-Based Start-Up
            1. 8.2.1.2.2.1 Choosing the VOUT Slew Rate
          3. 8.2.1.2.3 Select RSNS and CL Setting
          4. 8.2.1.2.4 Select Power Limit
          5. 8.2.1.2.5 Set Fault Timer
          6. 8.2.1.2.6 Check MOSFET SOA
          7. 8.2.1.2.7 Set UVLO and OVLO Thresholds
            1. 8.2.1.2.7.1 Option A
            2. 8.2.1.2.7.2 Option B
            3. 8.2.1.2.7.3 Option C
            4. 8.2.1.2.7.4 Option D
          8. 8.2.1.2.8 Power Good Pin
          9. 8.2.1.2.9 Input and Output Protection
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Option Addendum
    2. 11.2 Tape and Reel Information
    3. 11.3 Mechanical Data

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|28
Thermal pad, mechanical data (Package|Pins)
8.2.1.2.7.3 Option C

The minimum UVLO level is obtained by connecting the UVLO/EN pin to VIN as shown in Figure 8-5. Q1 is switched on when the VIN voltage reaches the POREN threshold (≊8.6 V). The OVLO thresholds are set using R3, R4. Their values are calculated using the procedure in Option B.

LM5066H UVLO = PORENFigure 8-5 UVLO = POREN