The LM5066H1 offers single gate drive capable of driving multiple MOSFETs in parallel. LM5066H2 features dual gate drive architecture that optimizes MOSFET selection for high power hot swap applications. GATE1 drives a single robust SOA MOSFET in dual gate configuration or multiple MOSFETs in single gate mode. With a 21μA gate source current, GATE1 provides controlled turn on for effective inrush current limiting or power limit based startup. A dV/dt capacitor can connect directly from GATE1 to GND for LM5066H1 or across SFT_STRT to GND for LM5066H2 to further manage inrush current. During current limiting or power limiting conditions, the device regulates GATE1 while keeping GATE2 off.

In dual gate operation, GATE2 drives multiple low R_DS(ON) MOSFETs for normal operation. To protect these MOSFETs, GATE2 turns off whenever V_DS exceeds 2V, preventing power stress during startup, short circuit conditions, or current/power limiting events. GATE2 activates only after GATE1 V_GS exceeds 8V and V_DS drops below 2V. The higher gate source current (130μA) enables rapid turn on of multiple parallel MOSFETs.

GATE1 and GATE2 are turned OFF for LM5066Hx if any of the below events occur,

• Current exceeds the current limit threshold after Over Current blanking and regulation fault timer expires

• Power dissipation in the MOSFET exceeds the power limit threshold and regulation fault timer expires

• Undervoltage or overvoltage conditions

• Circuit breaker or Short circuit protection

• Over temperature or damaged MOSFET detection or watchdog expiry faults

• PMBus Commands, OPERATION or POWER CYCLE command sets output disable

In steady state when any of the below conditions occur, GATE2 is turned OFF and GATE 1 remains ON or in regulation,

• V_DS exceeds 2V for any reason

• Start of Current limiting or power limiting operation

An internal charge pump supplies gate voltage to both outputs, producing approximately 13.5V at the gates under normal operation. During initial power up, a 10 mA pulldown prevents unwanted MOSFET activation from Miller capacitance effects.

During insertion time, both gates are held low by 10 mA pulldown currents. After insertion, GATE1 voltage modulates to maintain current and power within programmed limits while the TIMER capacitor charges. If limiting conditions resolve before TIMER reaches 3.9 V, the capacitor discharges and normal operation begins. If limiting persists until TIMER reaches 3.9 V, GATE1 pulls low until a retry occurs.

The LM5066Hx offers configurable gate pulldown strength (10 mA or 1.5 A) for various fault conditions, providing flexibility to match system requirements.