SLOSEB6D February   2025  – November 2025 LMH13000

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics for Low-Current Mode, MODE = 0
    6. 5.6 Electrical Characteristics for High-Current Mode, MODE = 1
    7. 5.7 Typical Characteristics
    8. 5.8 Parameter Measurement Information
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Constant Current (ICC)
      2. 6.3.2 Propagation Delay With Temperature
        1. 6.3.2.1 Calibration of Propagation Delay With Temperature
        2. 6.3.2.2 Start Pulse Directly From IOUT
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Optical Time-of-Flight System
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Automatic Power-Control Loop Using the LMH13000
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RQE|13
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.1 Layout Guidelines

Use the following recommendations to achieve nanosecond rise time on the output current. For dc applications and applications that require relaxed transient performance, the layout guidelines are able to be slightly deviated.

  • Placement of RSNUB and CSNUB:
    • Place RSNUB and CSNUB as close as possible to the device.
    • Any parasitic series inductance in the snubber path reduces the effectiveness of the snubber. Use low inductance components to enhance effectiveness.
    • Add two snubber circuits on either side of the IOUT and PGND pins (see Figure 7-4).
  • Capacitor bank placement:
    • A capacitor bank is required to provide fast transient currents to the VLD and PVDD supply pins.
    • Place the capacitor bank as close as possible to the VLD and PVDD pins.
    • The capacitor bank typically consists of a low-ESL capacitor as the first capacitor closest to the pin.
  • Connection between PVDD and AVDD:
    • PVDD and AVDD must be star connected. Add series ferrite beads and narrow traces to help minimize high-frequency noise and interference between the two pins. Both supplies must be at the same electrical potential.
    • Each supply must have dedicated decoupling capacitor to provide sufficient transient current.
  • Routing of EP and EN for the LVDS pins:
    • Route EP and EN differentially and terminate with a 100Ω resistance. Differential routing improves signal integrity and reduces electromagnetic interference (EMI).
  • IOUT trace design:
    • CBANK, VLD, LOAD, IOUT, and PGND must form a tight loop to reduce effect of trace inductance.
    • The IOUT trace must have a thick copper pour to handle high current and reduce trace inductance effectively.
    • In situations where the loop cannot be minimized, route the to and return parts of the VLD CBANK on top of each other. This routing is achieved by using top and second layers of the PCB to carry currents in the opposite direction. This layout technique enables reduction of common source inductance (see also Figure 7-7).
  • Thermal performance
    • Place thermal vias below the IOUT and PGND pins to dissipate heat efficiently.
    • A thermal plane on the bottom layer of the PCB acts as a excellent heat sink; however, addition of a plane or heat sink increases capacitance on the IOUT. This increase in capacitance results in increase of overshoot in the IOUT pulse.
    • If the overshoot is undesired, tune the snubber appropriately or increase the series damp resistance, RDAMP.