SLOSEB6D February   2025  – November 2025 LMH13000

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics for Low-Current Mode, MODE = 0
    6. 5.6 Electrical Characteristics for High-Current Mode, MODE = 1
    7. 5.7 Typical Characteristics
    8. 5.8 Parameter Measurement Information
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Constant Current (ICC)
      2. 6.3.2 Propagation Delay With Temperature
        1. 6.3.2.1 Calibration of Propagation Delay With Temperature
        2. 6.3.2.2 Start Pulse Directly From IOUT
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Optical Time-of-Flight System
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Automatic Power-Control Loop Using the LMH13000
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RQE|13
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.1.2 Detailed Design Procedure

LMH13000 Transmit Path Schematic With the LMH13000 Figure 7-2 Transmit Path Schematic With the LMH13000

Based on the required optical power and rise time, the V105Q121A-940 is considered as the laser for the transmit path. The IOUT of the LMH13000 is connected to the cathode of the laser because the device is a sink-current driver. The anode of the laser is connected to a bias voltage, VLD. The required optical power is 1.5W; using the optical output power graph from the laser diode data sheet, an IOUT of 2A is calculated. The MODE pin is tied to AVDD because the 2A IOUT is supported in high-current mode. The PD pin is tied to AGND.

VSET is set to 0.8V to set up an IOUT of 2A using the following equation. The VSET voltage is applied using a DAC through a 20kΩ series resistor.

Equation 6. I O U T   =   V S E T R S E T   ×   k   ;   k   =   50 k

The required VLD voltage is a function of minimum required VIOUT, VF and IOUT path inductance. The minimum VIOUT is inferred using the Electrical Characteristics tables.

Equation 7. V L D   =   M I N V I O U T   +   V F   +   L   ×   d I O U T d t   +   I O U T   ×   ( R L A S E R + R D A M P )

Where VF = forward bias voltage of the laser diode, L = LLASER + LTRACE, dIOUT = 2A and dt = 1ns.

See Figure 5-27 for the required MINVIOUT for a specific IOUT. As per Figure 5-27, MINVIOUT is ≅ 1V for an IOUT of 2A. For 2A pulse, VF = 1.85V (from the laser data sheet). Inductance, L (the sum of laser and board trace inductance), is estimated and measured to be approximately = 1.5nH. Adding these values results in a minimum required VLD of ≅ 6V (assuming RDAMP = 0Ω). For dc, slow-rise-time, current-output applications, the L × dIOUT / dt component is able to be made 0 in the previous equation.

To achieve a pulse duration of 2ns, a LVDS signal of > 250mV with a duration of 2ns is applied across the LVDS pins. Design the LVDS common-mode and differential voltage to be well within the maximum limits specified in the Electrical Characteristics.

This setup provides a preliminary guideline for generating a current pulse of 2A, with an on time of 2ns. To achieve a pulse train of a different frequency and duty cycle, simply apply the required logic signals (LVDS/CMOS/TTL) to the EP and EN pins.

LMH13000 Second-Order RLC Circuit for the IOUT Path Figure 7-3 Second-Order RLC Circuit for the IOUT Path

Observing the IOUT pulse response either in the electrical or optical domain gives the general direction required for tweaking of the circuit to achieve the required current-output response.

  • The increased VLD voltage enables a faster rise time due to the higher voltage available to set up current, across the board and laser inductance. However, with a higher VLD, the overshoot increases proportionally.
  • To achieve a critical response in the IOUT pulse, the goal of the design is to make zeta (ζ) = 1, for the second-order system shown in Figure 7-3. By adding a CSNUB much greater than CIOUT, the second-order circuit behaviors are determined mainly by the CSNUB value.
  • Equation 8. C S N U B   =   5   ×   C I O U T

    The CIOUT for the minimum VIOUT is found in Figure 5-12.

  • CSNUB calculates to approximately 300pF as CIOUT ≅ 62pF for VIOUT 6V.
  • Substituting value of CSNUB, LLASER+TRACE and RLASER in the following formula:
    Equation 9. ζ   =   R L A S E R   +   R D A M P +   R S N U B 2     ×   √ C S N U B L L A S E R + L T R A C E  
    Fine tune the RSNUB to achieve the correct balance of rise time and overshoot. Add a snubber on both sides of the IOUT (see Figure 7-6 and Figure 7-7) to make the snubber most effective.
  • If the overshoot and rise time balance is not satisfactory, an addition of a small-series damp resistor, RDAMP enables a reduced overshoot current-output response. The addition of a damping series resistor pushes the ζ towards or over 1, to tune the RLC circuit towards a critically damped response.

The Electrical Characteristics table states that the accuracy at room temperature for a 2A output current in MODE = 1 is about 5%. Therefore, when set to 2A, IOUT has the probability of not being accurate to exactly 2A, but is actually set to 2A ± 5%. This inaccuracy mandates adjusting VSET slightly greater than or less than 0.8V to bring IOUT to exactly 2A. After this adjustment, IOUT is accurate to 2A ±1.3% across temperature; see also the IOUT variation across temperature in Section 5.6.

For output pulses smaller than the settling time of IOUT, the peak amplitude is predominantly set by the overshoot value. In such cases, tune VSET to adjust for the peak overshoot value.