SLOSEB6D February 2025 – November 2025 LMH13000
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| IOUT DC PERFORMANCE | |||||||
| IOUT | Adjustable current(4) | VSET = 0.1V to 2V | TA = –40℃ to +125℃ | 0.25 | 5 | A | |
| IOUT accuracy | IOUT = 0.5A | ±10.5 | % | ||||
| IOUT = 2A | ±6 | ||||||
| IOUT = 5A | ±4 | ||||||
| IOUT variation | IOUT = 0.5A | TA = –40℃ to +125℃ | ±2.5 | % | |||
| IOUT = 2A | TA = –40℃ to +125℃ | ±1.3 | |||||
| IOUT = 5A | TA = –40℃ to +125℃ | ±0.9 | |||||
| MINVIOUT | Minimum VIOUT(1) | IOUT = 0.5A | TA = –40℃ to +125℃ | 0.7 | V | ||
| IOUT = 5A | TA = –40℃ to +125℃ | 2.2 | |||||
| ILEAK | Leakage current at IOUT | PD = 1 or LVDS = 0, | 0.35 | µA | |||
| TA = –40℃ to +125℃ | 100 | ||||||
| MAXVIOUT | Maximum VIOUT | 18 | V | ||||
| IOUT AC PERFORMANCE (RDAMP = 1Ω, LLOAD = 1nH), SEE Figure 5-31 | |||||||
| CIOUT | IOUT impedance | Parallel capacitance(2) | See Figure 5-12 | pF | |||
| LIOUT | IOUT impedance | Series inductance(3) | 100 | pH | |||
| IOUT noise | IOUT = 0.5A, integration bandwidth = 100MHz |
TA = –40℃ to +125℃ | 200 | µARMS | |||
| tr | IOUT rise time | IOUT = 2A, VLD = 6V | 0.5 | ns | |||
| TA = –40℃ to +125℃ | 0.6 | ||||||
| tf | IOUT fall time | IOUT = 2A, VLD = 6V | 0.5 | ns | |||
| TA = –40℃ to +125℃ | 0.7 | ||||||
| IOUT overshoot | IOUT = 2A, VLD = 6V | 20 | % | ||||
| IOUT undershoot | IOUT = 2A, VLD = 6V | 15 | % | ||||
| IOUT settling time | IOUT = 2A, 10% settling | 4 | ns | ||||
| TA = –40℃ to +125℃ | 6 | ||||||
| VSET (IOUT CONTROL PIN) | |||||||
| VSET | VSET pin voltage | For IOUT = 0.25A to 5A | 0.1 | 2 | V | ||
| k | Scaling factor for VSET to IOUT | IOUT = VSET / RSET × k | 50000 | ||||
| IOUT / VSET bandwidth | 600 | kHz | |||||
| LVDS INPUT | |||||||
| LVDS to IOUT propagation delay | IOUT = 2A | 9 | ns | ||||
| TA = –40℃ to +125℃ | 13 | ||||||
| IOUT = 5A | 9 | ||||||
| TA = –40℃ to +125℃ | 10 | ||||||
| Frequency (LVDS/TTL/CMOS) | 250 | MHz | |||||
| IOUT jitter | f < 250MHz, 50% duty cycle | 7 | ps | ||||
| POWER SUPPLY | |||||||
| Static quiescent current | LVDS = 0, VSET = 0.2V | 23.5 | mA | ||||
| TA = –40℃ to +125℃ | 24 | ||||||
| Dynamic quiescent current | ΔLVDS at 10MHz, IOUT = 5A | 50 | mA | ||||
| ΔLVDS at 200MHz, IOUT = 5A | 360 | ||||||