SLOSEB6D February   2025  – November 2025 LMH13000

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics for Low-Current Mode, MODE = 0
    6. 5.6 Electrical Characteristics for High-Current Mode, MODE = 1
    7. 5.7 Typical Characteristics
    8. 5.8 Parameter Measurement Information
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Constant Current (ICC)
      2. 6.3.2 Propagation Delay With Temperature
        1. 6.3.2.1 Calibration of Propagation Delay With Temperature
        2. 6.3.2.2 Start Pulse Directly From IOUT
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Optical Time-of-Flight System
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Automatic Power-Control Loop Using the LMH13000
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RQE|13
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3 Power Supply Recommendations

AVDD and PVDD are the two power pins for the LMH13000. Connect AVDD and PVDD to the same electrical potential. Provide separate decoupling capacitors to each pin.

During the LMH13000 power-up, both AVDD and PVDD are sequenced (ramped-up) together. A small mismatch in power-up timing due to the difference in decoupling capacitors is tolerated. Make sure that the MODE pin voltage < AVDD and PVDD for all conditions. To fulfill this condition, tie the MODE pin to AVDD or AGND at all times. Post AVDD and PVDD power up, other pins can be powered in any sequence.

Restrict the voltage on the IOUT to a maximum of 18V. This restriction includes any overshoot that occurs during output-current-pulse fall time. The VLD power-up sequence is not important, but TI recommends to power up VLD after AVDD and PVDD power up.