SNAS674C September   2015  – May 2025 LMK61E2

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics - Power Supply
    6. 5.6  LVPECL Output Characteristics
    7. 5.7  LVDS Output Characteristics
    8. 5.8  HCSL Output Characteristics
    9. 5.9  OE Input Characteristics
    10. 5.10 ADD Input Characteristics
    11. 5.11 Frequency Tolerance Characteristics #GUID-0535526F-DD03-4092-AF22-72C29F7682F3/SNAS6776645
    12. 5.12 Power-On/Reset Characteristics (VDD)
    13. 5.13 I2C-Compatible Interface Characteristics (SDA, SCL)
    14. 5.14 PSRR Characteristics
    15. 5.15 Other Characteristics
    16. 5.16 PLL Clock Output Jitter Characteristics #GUID-A72B6B2B-0279-4F5A-AC8C-45785B0FF568/SNAS6776369 #GUID-A72B6B2B-0279-4F5A-AC8C-45785B0FF568/SNAS6773735
    17. 5.17 Typical 156.25MHz Output Phase Noise Characteristics #GUID-00AE447B-502F-42A7-B85A-8E83BC487AD9/SNAS6777861 #GUID-00AE447B-502F-42A7-B85A-8E83BC487AD9/SNAS6776335
    18. 5.18 Typical 161.1328125 MHz Output Phase Noise Characteristics
    19. 5.19 Additional Reliability and Qualification
    20. 5.20 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Device Output Configurations
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Device Block-Level Description
      2. 7.3.2  Device Configuration Control
      3. 7.3.3  Register File Reference Convention
      4. 7.3.4  Configuring the PLL
      5. 7.3.5  Integrated Oscillator
      6. 7.3.6  Reference Doubler
      7. 7.3.7  Phase Frequency Detector
      8. 7.3.8  Feedback Divider (N)
      9. 7.3.9  Fractional Circuitry
      10. 7.3.10 Charge Pump
      11. 7.3.11 Loop Filter
      12. 7.3.12 VCO Calibration
      13. 7.3.13 High-Speed Output Divider
      14. 7.3.14 High-Speed Clock Output
      15. 7.3.15 Device Status
        1. 7.3.15.1 Loss of Lock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Interface and Control
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
      2. 7.5.2 Block Register Write
      3. 7.5.3 Block Register Read
      4. 7.5.4 Write SRAM
      5. 7.5.5 Write EEPROM
      6. 7.5.6 Read SRAM
      7. 7.5.7 Read EEPROM
    6. 7.6 EEPROM Map
  9. 8 Register Map
    1. 8.1 Register Descriptions
      1. 8.1.1  VNDRID_BY1 Register; R0
      2. 8.1.2  VNDRID_BY0 Register; R1
      3. 8.1.3  PRODID Register; R2
      4. 8.1.4  REVID Register; R3
      5. 8.1.5  TARGETADR Register; R8
      6. 8.1.6  EEREV Register; R9
      7. 8.1.7  DEV_CTL Register; R10
      8. 8.1.8  XO_CAPCTRL_BY1 Register; R16
      9. 8.1.9  XO_CAPCTRL_BY0 Register; R17
      10. 8.1.10 DIFFCTL Register; R21
      11. 8.1.11 OUTDIV_BY1 Register; R22
      12. 8.1.12 OUTDIV_BY0 Register; R23
      13. 8.1.13 PLL_NDIV_BY1 Register; R25
      14. 8.1.14 PLL_NDIV_BY0 Register; R26
      15. 8.1.15 PLL_FRACNUM_BY2 Register; R27
      16. 8.1.16 PLL_FRACNUM_BY1 Register; R28
      17. 8.1.17 PLL_FRACNUM_BY0 Register; R29
      18. 8.1.18 PLL_FRACDEN_BY2 Register; R30
      19. 8.1.19 PLL_FRACDEN_BY1 Register; R31
      20. 8.1.20 PLL_FRACDEN_BY0 Register; R32
      21. 8.1.21 PLL_MASHCTRL Register; R33
      22. 8.1.22 PLL_CTRL0 Register; R34
      23. 8.1.23 PLL_CTRL1 Register; R35
      24. 8.1.24 PLL_LF_R2 Register; R36
      25. 8.1.25 PLL_LF_C1 Register; R37
      26. 8.1.26 PLL_LF_R3 Register; R38
      27. 8.1.27 PLL_LF_C3 Register; R39
      28. 8.1.28 PLL_CALCTRL Register; R42
      29. 8.1.29 NVMSCRC Register; R47
      30. 8.1.30 NVMCNT Register; R48
      31. 8.1.31 NVMCTL Register; R49
      32. 8.1.32 NVMLCRC Register; R50
      33. 8.1.33 MEMADR Register; R51
      34. 8.1.34 NVMDAT Register; R52
      35. 8.1.35 RAMDAT Register; R53
      36. 8.1.36 NVMUNLK Register; R56
      37. 8.1.37 INT_LIVE Register; R66
      38. 8.1.38 SWRST Register; R72
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Jitter Considerations in Serdes Systems
      2. 9.2.2 Frequency Margining
        1. 9.2.2.1 Fine Frequency Margining
        2. 9.2.2.2 Coarse Frequency Margining
      3. 9.2.3 Design Requirements
        1. 9.2.3.1 Detailed Design Procedure
          1. 9.2.3.1.1 Custom Design With WEBENCH® Tools
          2. 9.2.3.1.2 Device Selection
          3. 9.2.3.1.3 VCO Frequency Calculation
          4. 9.2.3.1.4 Device Configuration
          5. 9.2.3.1.5 PLL Loop Filter Design
          6. 9.2.3.1.6 Spur Mitigation Techniques
            1. 9.2.3.1.6.1 Phase Detection Spur
            2. 9.2.3.1.6.2 Integer Boundary Fractional Spur
            3. 9.2.3.1.6.3 Primary Fractional Spur
            4. 9.2.3.1.6.4 Sub-Fractional Spur
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Verified Thermal Reliability
        2. 9.4.1.2 Best Practices for Signal Integrity
        3. 9.4.1.3 Recommended Solder Reflow Profile
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
9.2.3.1.4 Device Configuration

For this example, enter the desired output frequency and click on Generate Solutions. Select LMK61E2 from the solution list. To maximize the phase detector frequency using the simulation page of the WEBENCH Clock Architect Tool, the PLL R divider is set to 1, doubler is enabled and N divider is set to 50 for a PFD frequency of 100MHz. This results in a VCO frequency of 5GHz. At this point the design meets the output frequency requirements and design a loop filter can be made for the system and performance can be simulated on the clock output.