The I²C port on the LMK61E2 works as a target device and supports both the 100kHz standard mode and 400kHz fast mode operations. Fast mode imposes a glitch tolerance requirement on the control signals. Therefore, the input receivers ignore pulses of less than 50ns duration. The I²C timing is given in I²C-Compatible Interface Characteristics (SDA, SCL). The timing diagram is given in Figure 7-4.

Figure 7-4 I²C Timing Diagram

In an I²C bus system, the LMK61E2 acts as a target device and is connected to the serial bus (data bus SDA and lock bus SCL). These are accessed using a 7-bit target address transmitted as part of an I²C packet. Only the device with a matching target address responds to subsequent I²C commands. In soft pin mode, the LMK61E2 allows up to three unique target devices to occupy the I²C bus based on the pin strapping of ADD (tied to VDD, GND, or left open). The device target address is 10110xx (the two LSBs are determined by the ADD pin).

During the data transfer through the I²C interface, one clock pulse is generated for each data bit transferred. The data on the SDA line must be stable during the high period of the clock. The high or low state of the data line can change only when the clock signal on the SCL line is low. The start data transfer condition is characterized by a high-to-low transition on the SDA line while SCL is high. The stop data transfer condition is characterized by a low-to-high transition on the SDA line while SCL is high. The start and stop conditions are always initiated by the controller. Every byte on the SDA line must be eight bits long. Each byte must be followed by an acknowledge bit and bytes are sent MSB first. The I²C register structure of the LMK61E2 is shown in Figure 7-5.

Figure 7-5 I²C Register Structure

The acknowledge bit (A) or non-acknowledge bit (A’) is the 9th bit attached to any 8-bit data byte and is always generated by the receiver to inform the transmitter that the byte has been received (when A = 0) or not (when A’ = 0). A = 0 is done by pulling the SDA line low during the 9th clock pulse and A’ = 0 is done by leaving the SDA line high during the 9th clock pulse.

The I²C controller initiates the data transfer by asserting a start condition which initiates a response from all target devices connected to the serial bus. Based on the 8-bit address byte sent by the controller over the SDA line (consisting of the 7-bit target address (MSB first) and an R/W’ bit), the device whose address corresponds to the transmitted address responds by sending an acknowledge bit. All other devices on the bus remain idle while the selected device waits for data transfer with the controller.

After the data transfer has occurred, stop conditions are established. In write mode, the controller asserts a stop condition to end data transfer during the 10th clock pulse following the acknowledge bit for the last data byte from the target. In read mode, the controller receives the last data byte from the target but does not pull SDA low during the 9th clock pulse. This is known as a non-acknowledge bit. By receiving the non-acknowledge bit, the target knows the data transfer is finished and enters the idle mode. The controller then takes the data line low during the low period before the 10th clock pulse, and high during the 10th clock pulse to assert a stop condition. A generic transaction is shown in Figure 7-6.

Figure 7-6 Generic Programming Sequence

The LMK61E2 I²C interface supports Block Register Write/Read, Read/Write SRAM, and Read/Write EEPROM operations. For Block Register Write/Read operations, the I²C controller can individually access addressed registers that are made of an 8-bit data byte. The offset of the indexed register is encoded in the register address, as described in Table 7-1.