Design of all aspects of the LMK61E2 is simplified with software support that assists in part selection, part programming, loop filter design, and phase noise simulation. This design procedure provides a quick outline of the process.

1. Device Selection
   • The first step to calculate the specified VCO frequency given required output frequency. The device must be able to produce the VCO frequency that can be divided down to the required output frequency.
   • The WEBENCH Clock Architect Tool from TI aids in the selection of the right device that meets the designer output frequency and format requirements.
2. Device Configuration
   • There are many device configurations to achieve the desired output frequency from a device. However, the user must consider some optimizations and trade-offs.
   • The WEBENCH Clock Architect Tool attempts to maximize the phase detector frequency, use smallest dividers, and maximizes PLL charge pump current.
   • These guidelines below can be followed when configuring PLL related dividers or other related registers:
     • For lowest possible in-band PLL flat noise, maximize phase detector frequency to minimize N divide value.
     • For lowest possible in-band PLL flat noise, maximize charge pump current. The highest value charge pump currents often have similar performance due to diminishing returns.
     • For fractional divider values, keep the denominator at highest value possible to minimize spurs. Use higher order modulator wherever possible for the same reason.
     • The general guidance is to keep the phase detector frequency approximately between 10 × PLL loop bandwidth and 100 × PLL loop bandwidth. A phase detector frequency less than 5 × PLL bandwidth can be unstable and a phase.
3. PLL Loop Filter Design
   • Using the WEBENCH Clock Architect Tool to design your loop filter is recommended.
   • The desirable loop filter design and simulation can be achieved when custom reference phase noise profiles are loaded into the software tool.
   • While designing the loop filter, adjusting the charge pump current or N value can help with loop filter component selection. Lower charge pump currents and larger N values result in smaller component values but can increase impacts of leakage and reduce PLL phase noise performance.
   • For a more detailed understanding of loop filter design can be found in PLL Performance, Simulation, and Design (SNAA106).
4. Device Programming
   • The EVM programming software tool CodeLoader can be used to program the device with the desired configuration.