SLLS732A October   2006  – November 2019 SN65LBC174A-EP

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
    1.     Device Images
      1.      Logic Diagram (Positive Logic)
  4. 4Revision History
  5. 5Description (continued)
    1. 5.1 Pin Configuration and Functions
      1.      Pin Functions
    2. 5.2 Specifications
      1. 5.2.1 Absolute Maximum Ratings
      2. 5.2.2 ESD Ratings
      3. 5.2.3 Recommended Operating Conditions
      4. 5.2.4 Thermal Information
      5. 5.2.5 Electrical Characteristics
      6. 5.2.6 Switching Characteristics
      7. 5.2.7 Typical Characteristics
    3. 5.3 Parameter Measurement Information
    4. 5.4 Detailed Description
      1. 5.4.1 Overview
      2. 5.4.2 Functional Block Diagram
      3. 5.4.3 Feature Description
      4. 5.4.4 Device Functional Modes
    5. 5.5 Application and Implementation
      1. 5.5.1 Application Information
      2. 5.5.2 Typical Application
        1. 5.5.2.1 Design Requirements
        2. 5.5.2.2 Detailed Design Procedure
        3. 5.5.2.3 Application Curve
    6. 5.6 Power Supply Recommendations
    7. 5.7 Layout
      1. 5.7.1 Layout Guidelines
      2. 5.7.2 Layout Example
  6. 6Device and Documentation Support
    1. 6.1 Receiving Notification of Documentation Updates
    2. 6.2 Support Resources
    3. 6.3 Trademarks
    4. 6.4 Electrostatic Discharge Caution
    5. 6.5 Glossary
  7. 7Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DW|16
  • DW|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.2.5 Electrical Characteristics

over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VIK Input clamp voltage II = –18 mA –1.5 –0.77 V
VO Open-circuit output voltage Y or Z, No load 0 VCC V
|VOD(SS)| Steady-state differential output
voltage magnitude(2) 		No load (open circuit) 3 VCC V
RL = 54 Ω, See Figure 7 0.8 1.6 2.5
With common-mode loading, See Figure 8 0.8 1.6 2.5
ΔVOD(SS) Change in steady-state differential output voltage between logic states See Figure 7 –0.1 0.1 V
VOC(SS) Steady-state common-mode output voltage See Figure 9 2 2.4 2.8 V
ΔVOC(SS) Change in steady-state common-mode output voltage between logic states See Figure 9 –0.04 0.04 V
II Input current A, G, G –70 70 μA
IOS Short-circuit output current VTEST = –7 V to 12 V,
See Figure 13 		VI = 0 V –200 200 mA
VI = VCC
IOZ High-impedance-state output current EN at 0 V –50 50 μA
IO(OFF) Output current with power off VCC = 0 V –10 10 μA
ICC Supply current VI = 0 V or VCC,
No load		 All drivers enabled 25 mA
All drivers disabled 1.5
(1) All typical values are at VCC = 5 V and 25°C.
(2) The minimum VOD may not fully comply with TIA/EIA-485-A at operating temperatures below 0°C. System designers should take the possibility of lower output signal into account in determining the maximum signal transmission distance.