SLLS732A October   2006  – November 2019 SN65LBC174A-EP

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
    1.     Device Images
      1.      Logic Diagram (Positive Logic)
  4. 4Revision History
  5. 5Description (continued)
    1. 5.1 Pin Configuration and Functions
      1.      Pin Functions
    2. 5.2 Specifications
      1. 5.2.1 Absolute Maximum Ratings
      2. 5.2.2 ESD Ratings
      3. 5.2.3 Recommended Operating Conditions
      4. 5.2.4 Thermal Information
      5. 5.2.5 Electrical Characteristics
      6. 5.2.6 Switching Characteristics
      7. 5.2.7 Typical Characteristics
    3. 5.3 Parameter Measurement Information
    4. 5.4 Detailed Description
      1. 5.4.1 Overview
      2. 5.4.2 Functional Block Diagram
      3. 5.4.3 Feature Description
      4. 5.4.4 Device Functional Modes
    5. 5.5 Application and Implementation
      1. 5.5.1 Application Information
      2. 5.5.2 Typical Application
        1. 5.5.2.1 Design Requirements
        2. 5.5.2.2 Detailed Design Procedure
        3. 5.5.2.3 Application Curve
    6. 5.6 Power Supply Recommendations
    7. 5.7 Layout
      1. 5.7.1 Layout Guidelines
      2. 5.7.2 Layout Example
  6. 6Device and Documentation Support
    1. 6.1 Receiving Notification of Documentation Updates
    2. 6.2 Support Resources
    3. 6.3 Trademarks
    4. 6.4 Electrostatic Discharge Caution
    5. 6.5 Glossary
  7. 7Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DW|16
  • DW|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices including:

  • Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry.
  • Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible.
  • Place termination resistor as close as possible to the input pins (if end point node).
  • Keep trace lengths from input pins to bus as short as possible to reduce stub lengths and reflections on any nodes that are not end points of bus.
  • To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace.