The device is configured to have 20 dB analog gain and switch at 768kHz, by the resistor network on the GAIN/FSW pin 9.
I2C slave address is set to default 0x98, as a result of the two address pins (ADR1, pin 26 and ADR2, pin 20) set to ground.
In this setup a master clock is supplied to the device on pin 22 (SCLK). the device can also run with 3-wire I2S by setting the PLL registers as shown in the Clock Generation and PLL section.
When the device is configured to operate in 3-wire mode of operation where BCLK is used as reference to PLL (NO SCLK), TI recommends shorting PIN23 (BCLK) and PIN22 (SCLK) and configuring the device to use SCLK as PLL reference.