SLAS965D September   2013  – October 2018 TAS5766M , TAS5768M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Smart Amplifier Overview
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 AC Electrical Characteristics
    7. 6.7 Electrical Characteristics
    8. 6.8 Timing Requirements - I2C Bus Timing
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart SOA
      2. 7.3.2 Smart BASS
      3. 7.3.3 Smart Protection
      4. 7.3.4 Implementing a Real World Design
      5. 7.3.5 Modulation Schemes
        1. 7.3.5.1 BD-Modulation
        2. 7.3.5.2 1SPW-Modulation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Protection System
        1. 7.4.1.1 Over Current Protection
        2. 7.4.1.2 Thermal Protection
        3. 7.4.1.3 DC Protection
      2. 7.4.2 Reset and System Clock Functions
        1. 7.4.2.1 Power-On Reset Function
        2. 7.4.2.2 System Clock Input
      3. 7.4.3 System Clock PLL Mode
      4. 7.4.4 Clock Generation and PLL
      5. 7.4.5 PLL Calculation
      6. 7.4.6 Audio Data Interface
        1. 7.4.6.1 Audio Serial Interface
        2. 7.4.6.2 PCM Audio Data Formats and Timing
      7. 7.4.7 TAS576xM Audio Processing Options
        1. 7.4.7.1  Overview
        2. 7.4.7.2  miniDSP Instruction Register
        3. 7.4.7.3  Digital Output
        4. 7.4.7.4  Software
        5. 7.4.7.5  Process Flow
        6. 7.4.7.6  Zero Data Detect
        7. 7.4.7.7  Power Save Modes
        8. 7.4.7.8  XSMT Pin (Soft Mute/Soft Un-Mute)
        9. 7.4.7.9  External Power Sense Undervoltage Protection Mode
        10. 7.4.7.10 Recommended Power Down Sequence
          1. 7.4.7.10.1 XSMT = 0
          2. 7.4.7.10.2 Clock Error Detect
          3. 7.4.7.10.3 Planned Shutdown
    5. 7.5 Programming
      1. 7.5.1 I2C Interface and Slave Address
      2. 7.5.2 Slave Address
      3. 7.5.3 Register Address Auto-Increment Mode
      4. 7.5.4 Packet Protocol
        1. Table 18. Read / Write Operation – Basic I2C Framework
      5. 7.5.5 Write Register
        1. Table 19. Write Operation
        2. 7.5.5.1   Read Register
          1. Table 20. Read Operation
    6. 7.6 Register Maps
  8. 8 Applications and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Component Selection Criteria
      2. 8.1.2 Component Selection Impact on Board Layout, Component Placement, and Trace Routing
      3. 8.1.3 Amplifier Output Filtering
    2. 8.2 Typical Applications
      1. 8.2.1 Stereo Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Gain Setting and Output Switch Frequency
          2. 8.2.1.2.2 Gain Setting and Supply Voltage
          3. 8.2.1.2.3 DAC to AMP AC Coupling
          4. 8.2.1.2.4 Bootstrap Capacitors
        3. 8.2.1.3 BTL Application Curves
      2. 8.2.2 Mono/PBTL Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 PBTL Application Curves
      3. 8.2.3 QFN BTL Application Diagram
        1. 8.2.3.1 Design Requirements
  9. 9 Power Supply Recommendations
    1. 9.1 AVDD, DVDD, CPVDD Supply
    2. 9.2 GVDD Supply
    3. 9.3 PVCC, AVCC Power Supply
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Register Map Information
    1. 11.1 Detailed Register Map Descriptions
      1. 11.1.1 Register Map Summary
      2. 11.1.2 Page 0 Registers
        1. 11.1.2.1  Page 0 / Register 1 (Hex 0x01)
        2. 11.1.2.2  Page 0 / Register 2 (Hex 0x02)
        3. 11.1.2.3  Page 0 / Register 3 (Hex 0x03)
        4. 11.1.2.4  Page 0 / Register 4 (Hex 0x04)
        5. 11.1.2.5  Page 0 / Register 7 (Hex 0x07)
        6. 11.1.2.6  Page 0 / Register 8 (Hex 0x08)
        7. 11.1.2.7  Page 0 / Register 9 (Hex 0x09)
        8. 11.1.2.8  Page 0 / Register 10 (Hex 0x0A)
        9. 11.1.2.9  Page 0 / Register 12 (Hex 0x0C)
        10. 11.1.2.10 Page 0 / Register 13 (Hex 0x0D)
        11. 11.1.2.11 Page 0 / Register 20 (Hex 0x14)
        12. 11.1.2.12 Page 0 / Register 21 (Hex 0x15)
        13. 11.1.2.13 Page 0 / Register 22 (Hex 0x16)
        14. 11.1.2.14 Page 0 / Register 23 (Hex 0x17)
        15. 11.1.2.15 Page 0 / Register 24 (Hex 0x18)
        16. 11.1.2.16 Page 0 / Register 27 (Hex 0x1B)
        17. 11.1.2.17 Page 0 / Register 28 (Hex 0x1C)
        18. 11.1.2.18 Page 0 / Register 29 (Hex 0x1D)
        19. 11.1.2.19 Page 0 / Register 30 (Hex 0x1E)
        20. 11.1.2.20 Page 0 / Register 32 (Hex 0x20)
        21. 11.1.2.21 Page 0 / Register 33 (Hex 0x21)
        22. 11.1.2.22 Page 0 / Register 34 (Hex 0x22)
        23. 11.1.2.23 Page 0 / Register 35 (Hex 0x23)
        24. 11.1.2.24 Page 0 / Register 36 (Hex 0x24)
        25. 11.1.2.25 Page 0 / Register 37 (Hex 0x25)
        26. 11.1.2.26 Page 0 / Register 40 (Hex 0x28)
        27. 11.1.2.27 Page 0 / Register 41 (Hex 0x29)
        28. 11.1.2.28 Page 0 / Register 42 (Hex 0x2A)
        29. 11.1.2.29 Page 0 / Register 43 (Hex 0x2B)
        30. 11.1.2.30 Page 0 / Register 44 (Hex 0x2C)
        31. 11.1.2.31 Page 0 / Register 59 (Hex 0x3B)
        32. 11.1.2.32 Page 0 / Register 65 (Hex 0x41)
        33. 11.1.2.33 Page 0 / Register 66 (Hex 0x42)
        34. 11.1.2.34 Page 0 / Register 82 (Hex 0x52)
        35. 11.1.2.35 Page 0 / Register 83 (Hex 0x53)
        36. 11.1.2.36 Page 0 / Register 84 (Hex 0x54)
        37. 11.1.2.37 Page 0 / Register 85 (Hex 0x55)
        38. 11.1.2.38 Page 0 / Register 86 (Hex 0x56)
        39. 11.1.2.39 Page 0 / Register 87 (Hex 0x57)
        40. 11.1.2.40 Page 0 / Register 90 (Hex 0x5A)
        41. 11.1.2.41 Page 0 / Register 91 (Hex 0x5B)
        42. 11.1.2.42 Page 0 / Register 92 (Hex 0x5C)
        43. 11.1.2.43 Page 0 / Register 93 (Hex 0x5D)
        44. 11.1.2.44 Page 0 / Register 94 (Hex 0x5E)
        45. 11.1.2.45 Page 0 / Register 95 (Hex 0x5F)
        46. 11.1.2.46 Page 0 / Register 108 (Hex 0x6C)
        47. 11.1.2.47 Page 0 / Register 118 (Hex 0x76)
        48. 11.1.2.48 Page 0 / Register 119 (Hex 0x77)
        49. 11.1.2.49 Page 0 / Register 120 (Hex 0x78)
        50. 11.1.2.50 Page 0 / Register 121 (Hex 0x79)
      3. 11.1.3 Page 1 Registers
        1. 11.1.3.1 Page 1 / Register 2 (Hex 0x02)
        2. 11.1.3.2 Page 1 / Register 5 (Hex 0x05)
        3. 11.1.3.3 Page 1 / Register 6 (Hex 0x06)
        4. 11.1.3.4 Page 1 / Register 7 (Hex 0x07)
        5. 11.1.3.5 Page 1 / Register 8 (Hex 0x08)
      4. 11.1.4 Page 44 Registers
        1. 11.1.4.1 Page 44 / Register 1 (Hex 0x01)
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11.1.1 Register Map Summary

Page 0
Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
1 0x01 RSV RSV RSV RSTM RSV RSV RSV RSTR
2 0x02 RSV RSV RSV RQST RSV RSV RSV RQPD
3 0x03 RSV RSV RSV RQML RSV RSV RSV RQMR
4 0x04 RSV RSV RSV PLCK RSV RSV RSV PLLE
7 0x07 RSV RSV RSV DEMP RSV RSV RSV SDSL
8 0x08 RSV RSV G3OE MUTEOE G1OE G2OE RSV RSV
9 0x09 RSV RSV BCKP BCKO RSV RSV RSV LRKO
10 0x0A DSPG7 DSPG6 DSPG5 DSPG4 DSPG3 DSPG2 DSPG1 DSPG0
12 0x0C RSV RSV RSV RSV RSV RSV RBCK RLRK
13 0x0D RSV RSV RSV SREF RSV RSV RSV RSV
20 0x14 RSV RSV RSV RSV PPDV3 PPDV2 PPDV1 PPDV0
21 0x15 RSV RSV PJDV5 PJDV4 PJDV3 PJDV2 PJDV1 PJDV0
22 0x16 RSV RSV PDDV5 PDDV4 PDDV3 PDDV2 PDDV1 PDDV0
23 0x17 PDDV7 PDDV6 PDDV5 PDDV4 PDDV3 PDDV2 PDDV1 PDDV0
24 0x18 RSV RSV RSV RSV PRDV3 PRDV2 PRDV1 PRDV0
27 0x1B RSV DDSP6 DDSP5 DDSP4 DDSP3 DDSP2 DDSP1 DDSP0
28 0x1C RSV DDAC6 DDAC5 DDAC4 DDAC3 DDAC2 DDAC1 DDAC0
29 0x1D RSV DNCP6 DNCP5 DNCP4 DNCP3 DNCP2 DNCP1 DNCP0
30 0x1E RSV DOSR6 DOSR5 DOSR4 DOSR3 DOSR2 DOSR1 DOSR0
32 0x20 RSV DBCK6 DBCK5 DBCK4 DBCK3 DBCK2 DBCK1 DBCK0
33 0x21 DLRK7 DLRK6 DLRK5 DLRK4 DLRK3 DLRK2 DLRK1 DLRK0
34 0x22 RSV RSV RSV I16E RSV RSV FSSP1 FSSP0
35 0x23 IDAC_MSB7 IDAC_MSB6 IDAC_MSB5 IDAC_MSB4 IDAC_MSB3 IDAC_MSB2 IDAC_MSB1 IDAC_MSB0
36 0x24 IDAC_LSB7 IDAC_LSB6 IDAC_LSB5 IDAC_LSB4 IDAC_LSB3 IDAC_LSB2 IDAC_LSB1 IDAC_LSB0
37 0x25 RSV IDFS IDBK IDSK IDCH IDCM DCAS IPLK
40 0x28 RSV RSV AFMT1 AFMT0 RSV RSV ALEN1 ALEN0
41 0x29 AOFS7 AOFS6 AOFS5 AOFS4 AOFS3 AOFS2 AOFS1 AOFS0
42 0x2A RSV RSV AUPL1 AUPL0 RSV RSV AUPR1 AUPR0
43 0x2B RSV RSV RSV PSEL4 PSEL3 PSEL2 PSEL1 PSEL0
44 0x2C RSV RSV RSV RSV RSV CMDP2 CMDP1 CMDP0
59 0x3B RSV AMTL2 AMTL1 AMTL0 RSV AMTR2 AMTR1 AMTR0
65 0x41 RSV RSV RSV RSV RSV ACTL AMLE AMRE
66 0x42 ADLY7 ADLY6 ADLY5 ADLY4 ADLY3 ADLY2 ADLY1 ADLY0
82 0x52 RSV RSV RSV RSV G2SL3 G2SL2 G2SL1 G2SL0
83 0x53 RSV RSV RSV RSV G1SL3 G1SL2 G1SL1 G1SL0
84 0x54 RSV RSV RSV RSV MTSL3 MTSL2 MTSL1 MTSL0
85 0x55 RSV RSV RSV RSV G3SL3 G3SL2 G3SL1 G3SL0
86 0x56 RSV RSV GOUT5 GOUT4 GOUT3 GOUT2 RSV RSV
87 0x57 RSV RSV GINV5 GINV4 GINV3 GINV2 RSV RSV
90 0x5A RSV RSV RSV L1OV R1OV L2OV R2OV SFOV
91 0x5B RSV DTFS2 DTFS1 DTFS0 DTSR3 DTSR2 DTSR1 DTSR0
92 0x5C RSV RSV RSV RSV RSV RSV RSV DTBR_MSB
93 0x5D DTBR_LSB7 DTBR_LSB6 DTBR_LSB5 DTBR_LSB4 DTBR_LSB3 DTBR_LSB2 DTBR_LSB1 DTBR_LSB0
94 0x5E RSV CDST6 CDST5 CDST4 CDST3 CDST2 CDST1 CDST0
95 0x5F RSV RSV RSV LTSH RSV CKMF CSRF CERF
108 0x6C RSV RSV ADLM ADRM RSV RSV AMLM AMRM
118 0x76 BOTM RSV RSV RSV PSTM3 PSTM2 PSTM1 PSTM0
119 0x77 RSV RSV GPIN5 RSV 3 2 RSV RSV
120 0x78 RSV RSV RSV AMFL RSV RSV RSV AMFR
121 0x79 RSV RSV RSV RSV RSV RSV RSV DAMD
Page 1
Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
2 0x02 RSV RSV RSV LAGN RSV RSV RSV RAGN
5 0x05 RSV RSV RSV RSV RSV RSV UEPD UIPD
6 0x06 RSV RSV RSV RSV RSV RSV RSV AMCT
7 0x07 RSV RSV RSV AGBL RSV RSV RSV AGBR
8 0x08 RSV RSV RSV RBGF RSV RSV RSV RSV
Page 44
Dec Hex b7 b6 b5 b4 b3 b2 b1 b0
1 0x01 RSV RSV RSV RSV ACRM AMDC ACRS ACSW