The TAS576xM requires a system clock to operate the digital interpolation filters and advanced segment DAC modulators. The system clock is applied at the SCLK input (pin 12) and supports up to 50MHz. The TAS576xM system-clock detection circuit automatically senses the system-clock frequency. The Smart AMP processing block only supports 44.1 kHz and 48kHz sampling rates even though the hardware supports all the common audio sampling frequencies in the bands of 8 kHz, 16 kHz, (32 kHz–44.1 kHz–48kHz), (88.2 kHz–96 kHz), (176.4 kHz–192 kHz), and 384 kHz with ±4% tolerance.
Values in the parentheses are "grouped" when detected, e.g. 88.2 kHZ and 96 kHz are detected as "double rate", 32 kHz, 44.1 kHz and 48 kHz will be detected as "single rate". The sampling frequency detector sets the clock for the digital filter, Delta Sigma Modulator (DSM) and the Negative Charge Pump (NCP) automatically. Table 2 shows examples of system clock frequencies for common audio sampling rates.
SCLK rates that are not common to standard audio clocks, between 1 MHz and 50 MHz, are only supported in software mode by configuring various PLL and clock-divider registers. This programmability allows the device to become a clock master and drive the host serial port with LRCLK and BCLK, from a non-audio related clock (for example, using 12 MHz to generate 44.1 kHz (LRCLK) and 2.8224 MHz (BCLK) )
Figure 33 shows the timing requirements for the system clock input. For optimal performance, use a clock source with low phase jitter and noise.
|SAMPLING FREQUENCY||SYSTEM CLOCK FREQUENCY (fSCLK) (MHz)|
|128 fs||192 fs||256 fs||384 fs||512 fs||768 fs||1024 fs|
|tSCY||System clock pulse cycle time||20||1000||ns|
|tSCLKH||System clock pulse width, High||8||ns|
|tSCLKL||System clock pulse width, Low||9||ns|