The system clock PLL mode allows designers to use a simple 3-wire I2S audio source when driving the output. The 3-wire source reduces the need for a high frequency SCLK, making PCB layout easier, and reduces high frequency electromagnetic interference.
The user must set all the PLL registers and clock divider registers for referencing BCLK. See Clock Generation and PLL for more information.
|Sample f (kHz)||BCLK (fS)|