SLAS965D September 2013 – October 2018 TAS5766M , TAS5768M
PRODUCTION DATA.
Dec | Hex | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
---|---|---|---|---|---|---|---|---|---|
9 | 0x09 | RSV | RSV | BCKP | BCKO | RSV | RSV | RSV | LRKO |
Reset Value | 0 | 0 | 0 |
RSV | Reserved | ||||||||
Reserved. Do not access. | |||||||||
BCKP | BCK Polarity | ||||||||
This bit sets the inverted BCK mode. In inverted BCK mode, the DAC assumes that the LRCK and DIN edges are aligned to the rising edge of the BCK. Normally they are assumed to be aligned to the falling edge of the BCK. | |||||||||
Default value: 0 | |||||||||
0: Normal BCK mode | |||||||||
1: Inverted BCK mode | |||||||||
BCKO | BCK Output Enable | ||||||||
This bit sets the BCK pin direction to output for I2S master mode operation. In I2S master mode the device outputs the reference BCK and LRCK, and the external source device provides the DIN according to these clocks. Use Page 0 / Register 32 to program the division factor of the SCK to yield the desired BCK rate (normally 64FS) | |||||||||
Default value: 0 | |||||||||
0: BCK is input (I2S slave mode) | |||||||||
1: BCK is output (I2S master mode) | |||||||||
LRKO | LRCLK Output Enable | ||||||||
This bit sets the LRCK pin direction to output for I2S master mode operation. In I2S master mode the device outputs the reference BCK and LRCK, and the external source device provides the DIN according to these clocks. Use Page 0 / Register 33 to program the division factor of the BCK to yield 1FS for LRCK. | |||||||||
Default value: 0 | |||||||||
0: LRCK is input (I2S slave mode) | |||||||||
1: LRCK is output (I2S master mode) |