SPRSP96A March 2024 – September 2024 TDA4AEN-Q1 , TDA4VEN-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Table 6-122, Figure 6-104, Table 6-123, and Figure 6-105 present timing requirements and switching characteristics for OSPI0 Tap SDR Mode.
NO. | MODE | MIN | MAX | UNIT | ||
---|---|---|---|---|---|---|
O19 | tsu(D-CLK) | Setup time, OSPI0_D[7:0] valid before active OSPI0_CLK edge | No Loopback | (15.4 - (0.975T(1)R(2))) | ns | |
O20 | th(CLK-D) | Hold time, OSPI0_D[7:0] valid after active OSPI0_CLK edge | No Loopback | (- 4.3 + (0.975T(1)R(2))) | ns |
NO. | PARAMETER | MODE | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
O7 | tc(CLK) | Cycle time, OSPI0_CLK | 20 | ns | ||
O8 | tw(CLKL) | Pulse duration, OSPI0_CLK low | ((0.475P(1)) - 0.3) | ns | ||
O9 | tw(CLKH) | Pulse duration, OSPI0_CLK high | ((0.475P(1)) - 0.3) | ns | ||
O10 | td(CSn-CLK) | Delay time, OSPI0_CSn[3:0] active edge to OSPI0_CLK rising edge | ((0.475P(1)) + (0.975M(2)R(4)) - 1) | ((0.525P(1)) + (1.025M(2)R(4)) + 1) | ns | |
O11 | td(CLK-CSn) | Delay time, OSPI0_CLK rising edge to OSPI0_CSn[3:0] inactive edge | ((0.475P(1)) + (0.975N(3)R(4)) - 1) | ((0.525P(1)) + (1.025N(3)R(4)) + 1) | ns | |
O12 | td(CLK-D) | Delay time, OSPI0_CLK active edge to OSPI0_D[7:0] transition | - 4.25 | 7.25 | ns |